[SI-LIST] Re: adjacent power plane spacing with sensitive power nodes
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Ignas Mikulevicius <mikulevi@xxxxxxxxx>
- Date: Fri, 09 Oct 2009 18:13:13 -0400
Yes. I'd suggest a quick turn fabrication of a board with an additional
layers to ground reference the power fills and isolate them from each other.
Ignas Mikulevicius wrote:
> Hello,
> First, some background:
> I have a PCB design that is experiencing some jitter issues that we are
> trying to get to the bottom of. It is a PCI Express design utilizing a
> Xilinx FPGA. The PCI Express transceivers are powered by 1.0V core
> circuitry, and 1.2V circuitry for the actual transmitter and the PLL. The
> core and the PLL circuitry are extremely sensitive to noise.
> One theory brought up was that we might be getting noise coupled into these
> sensitive nodes from adjacent power planes. The nodes are implemented as
> mini-planes on various layers of a 12 layer PCB.
> For example, one of the PLL mini islands is on layer 8, with a +12V plane on
> layer 7, with only a 3.4 mil spacing between the planes. There is no
> adjacent ground plane, only a signal plane on layer 9, which is 12 mils
> away. Similarly, layer 12 contains the 1.0V core mini-island as well as the
> 1.2V transmitter power supply mini-plane. Layer 11 is flooded with +3.3V,
> with a 2.9 mil separation from layer 12.
>
> *My question: Is it possible that noise on the +12V and +3.3V planes is
> coupling into the sensitive transceiver nodes and causing jitter?*
>
> My initial opinion was that any ripple on the voltage planes would be too
> small to actually couple into an adjacent plane, but maybe I am wrong? I
> have read some of the archived posts considering similar topics, but did not
> seem to find a definitive response.
> Thank you very much in advance,
> Ignas M.
>
>
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Scott McMorrow
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