[SI-LIST] Re: about split plane
- From: "George Tang" <gtang@xxxxxxxx>
- To: "Perry Qu" <Perry.Qu@xxxxxxxxxxx>
- Date: Wed, 19 Jun 2002 17:08:57 -0700
Perry,
When you say plane inductance, are you talking about the inductance seen by
the power and ground current or the inductance seen by the signal current
referencing to the plane? The power and ground plane inductance can be
minimized by the dielectric thickness in between the planes. The signal
current inductance can be measured by driving a TDR signal down the trace.
My measurements show that if you keep the width of copper on the plane in
between the antipads to be 3 times the height of the trace above the plane,
you should not see much impedance mismatches.
Regards,
George
-----Original Message-----
From: Perry Qu [mailto:Perry.Qu@xxxxxxxxxxx]
Sent: Wednesday, June 19, 2002 5:52 AM
To: gtang@xxxxxxxx
Cc: si-list
Subject: Re: [SI-LIST] Re: about split plane
George,
Thank you for your suggestions. I tried to put ground vias/decoupling caps
near
noisy signal vias, however, it's pretty much limited by the board space and
the
density of the board.
On another note, larger antipads have the benefit of less coupling between
via
and plane. The side effect is that the plane is also more cheezy when using
large antipad and thus increase the inductance, especially under BGAs.
Wonder
whether there is any study done on this.
Regards
Perry
George Tang wrote:
> To avoid generating parallel plate mode noises, you should place a ground
> via next to your signal via and use large power plane antipads. Use a
field
> solver to determine the dimensions of via, spacing, and antipad sizes.
> Power filtering is very important when you route power in long strips.
> Avoid resonance due to back-driving on these strips. With careful
planning,
> it should work.
>
> George Tang
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Perry Qu
> Sent: Tuesday, June 18, 2002 8:38 AM
> To: si-list
> Subject: [SI-LIST] about split plane
>
> Hello, everyone:
>
> I need some comments about implementation of split plane in our design.
> The split plane is used to supply core voltage for some ICs (e.g.,
> 1.5/1.8V). My current design rule for PCB layout is to use long strip
> to route from DC power supply to the device, so that only the IC who
> needs the core voltage is covered, and avoid spread the core voltage
> plane across the PCB. My consideration is that, when we spread the core
> voltage plane, there will be a lot of signal vias goes through thus
> generating parallel-plate mode noise between core plane and ground.
>
> On the other hand, I need to consider the voltage drop due to the copper
> loss for the long strip. I will do some simple esimation of resistive
> loss of copper strip based on thickness and strip width/length. As long
> as it satisfy my tolerance, I think it will be ok.
>
> Anything I missed ?
>
> BTW, I have taken care of the potential problem of routing over the gap
> by place ground plane immediately next to split plane in my stackup.
>
> Thanks in advance.
>
> --
> Perry Qu
>
> Product Integrity | 600 March Road
> Alcatel Canada | Ottawa, ON K2K 2E6, Canada
>
> DID: (613) 7846720 | FAX: (613) 5993642
>
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--
Perry Qu
Product Integrity | 600 March Road
Alcatel Canada | Ottawa, ON K2K 2E6, Canada
DID: (613) 7846720 | FAX: (613) 5993642
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