[SI-LIST] Re: about n-well parameters in standard 0.18um logic cmosprocess
- From: Sandy Taylor <cmos@xxxxxxxxxxxxxx>
- To: mike_bihan@xxxxxxxxxxxx
- Date: Tue, 11 Feb 2003 10:17:29 -0800
Bi,Hai
The N-well conductivity in a digital process is not very well speced.
Most foundries will have very loose tolerances on this parameter
to allow them some flexibility to tweak the P device implants.
Most digital designs have some analog circuits for PLLs and IOs,
but even in those cases, if they use the N-well as a resistor
they try to rely on matching of sets of resistors,
not the exact value of the resistance.
Foundries may spec the N-well resistivity tolerance anywhere from +/- 20%=
all the way up to +/- 50%. The tolerances in a set of wafers from
a given recipe will be tighter, but the foundry will want to keep
the option of tweaking things out from under you. Sorry.
The thickness is typically better controlled than the resistivity.
In a 0.18u process the nominal resistance will be somewhere in the
range of 300 - 3000 ohms per square with a thickness somewhere
in the range of 0.6 to 1.2u. Digital designers do not care about
the N-well resistance, just the final FET parameters, which are
the result of a set of implants, of which the N-well is just one.
I am sorry to say that you are in a bit of a bind if this is a critical
parameter. I hope that the volume of your product is sufficient
that the foundry takes notice and gives you special attention.
Then you may be able to get tighter spec.
Sandy Taylor
CMOS Solutions
Olga Wa.
Bi Han wrote:
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> I have a question about the 'thickness' and 'conductivity' parameters o=
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> N-well in standard 2-well 0.18um CMOS Logic process, thanks!=20
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> These two parameters are very critical for the performance of RF passiv=
e parameters. thanks again!
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> brief info will also be helpful!
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> Bi,Hai =20
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> SJTU, Emlab
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