[SI-LIST] Re: XTK analysis-help

  • From: "Wilco Hamhuis" <w.hamhuis@xxxxxxxxxxx>
  • To: <sivakumar@xxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 7 Mar 2002 09:56:14 +0100

Hello Sivakumar,

WARNING 75: This only occurs on differential pins or series devices.
Apparently you don't have a pin capacitance from the package for your
resistor defined (CEFF). According to the XTK manual isf2xtk is the process
of being enhanced to generate capacitance values for both pins of a series
device. So far I haven't seen that implementation, but to be sure you could
check this with the Innoveda guys.

WARNING 712: apparently there is something in your (IBIS?) model which gives
XTK the idea that it is a current controlled model. For example if it is an
Emitter Coupled Logic (ECL) component. If this is the case, add the
following line to your model (in the DRIVERSPEC section):

CURRENT_CONTROL_MODE

V5.2 indicates the XTK version from which you can use this statement.
Current version is 6.8. If your component isn't current controlled, you can
forget this warning. If you want more info about the CURRENT_CONTROL_MODE,
check the manual xtk_user.pdf, page 179.

Both warnings shouldn't affect the result of your simulation, I have seen
these before and the results are reliable. You can disable these kind of
warnings.

in XTK: options > defaults > disable report warnings
in Scratchpad (ePD 2.0): options > preferences > analyzer > defaults >
disable report warnings

Kind regards,
Wilco Hamhuis
HSSD consulting engineer


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Sivakumar S. - CTD,
Chennai.
Sent: Thursday, March 07, 2002 8:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] XTK analysis-help



Hi Gurus,
        While doing the SI analysis in XTK i have got the following
warnings.

        WARNING 75: Pin name not found for part R1 1_2. This prevents
package capacitance connection
        WARNING 712: <Out1 Output> <Out1 Output> indicates V5.2-
auto-current control.
        If you wish this to be a current control model (ECL) you MUST
        use the CURRENT_CONTROL_MODE command in the .mod file.

    This resistor model used is the default resistor model available with
XTK.  Though i am getting the results, i don't know  whether the result is
correct or not. I have captured this warning message from scratchpad. But i
am getting the same warning message  while using the *.asc file in XTK .
      I want to clear this warning message.Could anybody suggests me a way
to solve this issue?.

thanks and regards,
Sivakumar.S



-----Original Message-----
From: Bill Hargin [mailto:billh@xxxxxxxxxxxxxxxxxxxxxxx]
Sent: Thursday, March 07, 2002 12:35 AM
To: davem@xxxxxxxxxx; Robison_M@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: lee richey course etc



Hi Dave:

I would recommend e-mailing your request to him at info@xxxxxxxxxxxxxxxxx

I'm sure he would cut you a reasonable deal on replacing the course
materials.

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com



> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Dave Macemon
> Sent: Wednesday, March 06, 2002 10:50 AM
> To: Robison_M@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: lee richey course etc
>
>
>
>
> SiQual also offers classes in Signal Integrity.
>
> http://www.siqual.com/training/index.html
>
> regards
>
> davem
>
>
> At 12:43 PM 3/6/2002 -0600, Michael_Greim@xxxxxxxx wrote:
>
> >I thought Ed Sayre and crew at NESA offered
> >a very comprehensive set of classes.
> >
> >         http://www.nesa.com/engsem.html
> >
> >MG
> >
> >-----Original Message-----
> >From: Robison Michael R CNIN [mailto:Robison_M@xxxxxxxxxxxxxx]
> >Sent: Wednesday, March 06, 2002 12:39 PM
> >To: 'si-list@xxxxxxxxxxxxx'
> >Subject: [SI-LIST] lee richey course etc
> >
> >
> >
> >hello,
> >
> >i took lee richey's two-day signal integrity design
> >course at the PCB West last year and learned quite
> >a bit.  but i have lost the course material and books.
> >can i buy that somewhere?
> >
> >i need to learn more about designing PCB's with signal
> >integrity in mind.  i'd like to take a series of two-
> >to five-day courses and bring myself up to speed on this.
> >i've got a BSEE now and my background is digital testing
> >(i more or less hack my way thru the signal integrity
> >issues i face now).  i would appreciate any suggestions
> >you folks might have.
> >
> >i am aware that johnson offers some courses, and gigatest
> >too.
> >
> >thanks, miker
> >
> >
> >------------------------------------------------------------------
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>
> ===
> Dave Macemon
> SiQual, A division of Stilwell Baker
> davem@xxxxxxxxxx
> phone (503)885-1231
> fax     (503)885-0550
> http://www.siqual.com/
>
> ------------------------------------------------------------------
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