[SI-LIST] Re: Would you follow the overshoot specs of the datasheet?
- From: V S <for_si2003@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 27 Jul 2008 07:44:47 -0700 (PDT)
Practically, there is always a tussle between the si designer giving out the
rules to follow and the PCB designer finding it difficult to implement. The
solution lies in PCB designers learning the SI of SI engineer learning the PCB
design so that he can know the tradeoffs and limitations. If we are violating
the length specs in DDR2 routing we must know by how much margin and what will
be its implications.
Vikas Shukla
http://referencedesigner.com
--- On Sat, 7/26/08, steve weir <weirsi@xxxxxxxxxx> wrote:
> From: steve weir <weirsi@xxxxxxxxxx>
> Subject: [SI-LIST] Re: Would you follow the overshoot specs of the datasheet?
> To: "liuluping 41830" <liuluping@xxxxxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx, wangyongjin@xxxxxxxxxx
> Date: Saturday, July 26, 2008, 3:31 PM
> The detrimental effects of repeated overshoot violations
> have been
> discussed here at length in the past. My advice is that if
> you care
> about the reliability of your product, then limit
> overvoltage stress
> applied to the parts you use.
>
> Steve.
> liuluping 41830 wrote:
> > Hi all:
> >
> > This questions comes from yesterday's topic
> "DDR2 Trace Length Margin" which Jeff, Brian,Tom
> and many experts give very wonderful explains. Maybe the
> main problem is whether to follow the very tight specs ,
> length mathch is one aspect,and the overshoot is another
> one which is often more trouble to deal.
> > For example , a chip which contains 667Mbps DDR2
> and 33MHz PCI interfaces ,the datasheet said that all the
> overshoot on the digital interface should less than
> +/-0.7V,in despite of
> > the frequency,overshoot time ,would you follow this
> spec? How do you thinks about this?
> >
> > Regards,
> >
> > LIU Luping
> >
> >
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