[SI-LIST] Re: Wired-AND VS Wired-OR logic

From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
To: <Anand.Kuriakose@xxxxxxxxxx>
Date: Wed, 24 Apr 2002 12:19:32 -0400

> I have seen many documents refering to the above scenario as wired-OR
logic. It
> doesnt make sense. Also the PCI spec 2.2, sec2.1 refers to O/D signals
(ex INTX#
> and SERR#) as to be capable of introducing wired-OR logic.
 
When the signals are low-true (and for PCI, that's what the "#" symbol
means), then this connection performs the function of an OR gate.  When
either open-drain output is true (LOW), the combined output is also true
(LOW).

Such open-collector or open-drain drivers are often used with signals
that are low-true, which is why they become wired-OR rather than
wired-AND.

ECL's emitter-follower outputs were the opposite (active pull-up,
passive pull-down), so high-true ECL signals that are connected together
form a wired-OR function.

> Also one more question.  When it comes to wired-AND logic, only one
device can
> assert its output low. We cannot have more than one device asserting
its output
> low simultaneously. Am i right in saying so.
 
No.  The whole point of this, as an AND or OR gate function, is that any
or all can drive high or low simultaneously.

There are consequences of course, which you need to understand.  One of
them (which is more likely with an ECL wired-OR connection due to the
typically fast edge rate in BOTH directions) is that there can be a
glitch when one driver de-asserts while others stay asserted.  You might
think the net stays asserted, but there can be a transient that
momentarily reverses the assertion until the load current re-distributes
among the remaining outputs.

Andy



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[SI-LIST] Re: Wired-AND VS Wired-OR logic

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