[SI-LIST] Wirebond models for on-chip PDN characterization
- From: Allan Wang <allanw@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 6 Feb 2012 17:38:52 -0500
Hi all,
I'm a student researching a different topology for an on-chip PDN. To test,
we are able to get a very small (1mm x 1mm) 45nm test chip sent out for
fabrication in the next couple of months. The chip will have wirebonds. I'd
like to know if anyone has some pointers or papers on designing such a test
chip. I've already read this 2010 Altera paper [1] which seems to cover
most of it.
I have a few questions about the design:
1)
I'm planning on having:
1) Ring-oscillator VCO for generating a clock signal to feed into a bank of
inverters for load simulation. (or should I use T flip-flops like the
Altera paper?)
I'd appreciate any advice you guys can give me. Thanks.
Allan Wang
Carnegie Mellon University
[1] http://www.altera.com/literature/cp/cp-01060-pdn-noise.pdf
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