> Jim, >=20 > In regard to your comment: "Series termination > shoulkd NEVER be used wher the path is going to more > than one input i.e bus configuration.". The ATA/IDE > interface used in PCs is series terminated at the > source and is bussed to two loads on data and > strobe lines. The number of working systems in the > field is in the millions (every PC that has 2 > drives). The value of the series termination is a > great consideration (in ATA it is 22-50ohms). >=20 > So series termination in busses can work. Though, I > recommend a thorough understanding of the system > before employing this technique. >=20 >=20 > Charles Hill, consultant I concur. In theory, I agree that it's not "nice", but I've seen series te= rminations (with no parallel termination at the far end) used successfull= y in designs where there were multiple inputs on a trace. "Never" sounds= neat but as with most good rules, there are exceptions. I also agree with the caveats. In the examples I remember, the system was = running at a low clock frequency and all the inputs (not more than 3 in t= hat case) were close to each other at the end of a long trace. It was of= a daisy-chain topology, i.e. there were no branches on the trace, to min= imize the impedance discontinuities and reflections. The inputs had high= impedance. Of course, one gotta think twice, even thrice, before doing = this on a clock signal. Sandor --- Sandor Daranyi Snr Design Engineer Aristocrat Technologies Australia ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu