[SI-LIST] Re: Why no timing model available unitl now?
- From: "Tom Biggs" <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
- To: <peter.zhu@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 22 Nov 2006 09:20:37 -0800
There is a timing model called "STAMP". It is used by Mentor's Tau
board-level timing analysis tool. I think Xilinx tools can create STAMP
models. I think there is some Synopsis tool that can create them too.=20
I've never used it. I think most people tend to do home-grown
spreadsheet timing analysis.
-tom
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Peter Zhu (Zhu Yonghui)
Sent: Wednesday, November 22, 2006 5:18 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Why no timing model available unitl now?
In some sense, timing is more important than SI problem in digital
design. In high speed design, timing problem is more popular than SI
problem. I am very puzzled why there is no timing mode for simulation in
industry until now. We have to manually calculate the time margin from
the parameters on the datasheet. Why industry can not establish such a
model that contain timing parameters? If such timing mode combined with
SI mode(IBIS, SPICE) to simulate the circuit, It's really a big exciting
news to hardware design engineer.
Anybody has some info about such model standard? I really hope it can be
popular as current IBIS model.
=20
Thanks
Peter zhu
Continuous Computing China
Tel: 0755-26630888-6943
Fax: 0755-266630822
Mobile: 13823605271
=20
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=20
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