[SI-LIST] Re: Why is capacitor with high ESR
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 7 Dec 2004 18:30:22 -0800
Steve,
I think you can read my mind.
Zhangkun,
The devil is in the detail. I am almost certain you can construct case 6),
force your signals to reference the power planes and see magical improvement
using high ESR caps, thin core power/gnd plane etc etc. But that's just
academic unless you can show ground stitching in case 7) is worst than 6)
when the signal is properly referencing to ground only (with proper
decoupling on die).
You can always construct an ill-formed stack up and generate excessive noise
and justify any exotic solutions you need to fix it. So comparing 5,6 and 7
will be important.
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Tuesday, December 07, 2004 4:49 PM
To: zhang_kun@xxxxxxxxxx; si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: istvan.novak@xxxxxxxxxxxxxxxx; Chris.Cheng@xxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Why is capacitor with high ESR
Zhangkun, some comments-
At 07:46 AM 12/8/2004 +0800, zhangkun 29902 wrote:
>Dear all
>
>This morning, I spend half one hour to review all the mail about this
>topic. According to my experience, there is the following views:
> 1.Dency via will not absorb or scatter the EM energy. We have made
> testing PCB to study this problem. When there is no decoupling caps, the
> dency via will affect the resonance. While there is decoupling caps on
> the PCB, the effect of dency via could be ignored. In DesignCon 2004, we
> have proposed one paper.
Please forgive me for the language issue, do you mean densely populated
vias when you say "dency via?" If so, this would again depend on the
stack-up. If your test case had Vcc on an outside layer, then ground
stitch vias without decoupling capacitors would leave an open cavity.
> 2.Via along the edge of PCB will not help to eliminate the far field
> EMI. The via has no effect on reflecting EM energy unless the power and
> ground plane is connected by via. The voltage source will be shorted. We
> have made testing PCB to study this problem.
For any structure that the via leaves open, agreed. However one could
construct as Chris suggested with ground on the outside plane layers, in
which case the via fence does create a screen. For Vcc on the outside it
is only as good as the inductance loop through the local decoupling
capacitors.
> 3.Steve and Chris have proposed seven cases about the PCB decoupling.
> We have measured almost the seven cases. The result is that the caps with
> high ESR help on eliminate power ground noise.
Well, I am not surprised, but am most interested in your test case set-ups
and data for any comparative 4/5/6/7, especially 5 and 6.
> 4.I have done some simulation about SI+PI. I do not see any great
> difference when the signal referenced to power or ground. There is a
> little difference because of the displacement current. I think power and
> ground are same but the voltage potential.
The issue is that when you reference to power, you can excite the resonant
cavity formed by the power and ground layers.
>Best Regards
>
>Zhangkun
>2004.12.8
Steve
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