[SI-LIST] Re: Why is capacitor with high ESR
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'''Si-List ' ' '" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 6 Dec 2004 18:06:42 -0800
I think digging into the last paragraph is 2 hard 4 me. Have a great evening
and I am done with my holiday mood entertainment ;-D.
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Monday, December 06, 2004 5:55 PM
To: Chris.Cheng@xxxxxxxxxxxx; '''Si-List ' ' '
Subject: Re: [SI-LIST] Re: Why is capacitor with high ESR
Chris, it seems that we have good agreement on almost all points but
somehow seem to still disagree! In the present environment, I feel that
DET is not something that is economically practical. So my interest in
discussing it is only for the technical performance. In that context it
really doesn't matter that there are quite effective means for realizing
systems that pass emissions and perform reliably. they don't take away
from DET and DET doesn't take away from them, because I don't see it
getting deployed.
I agree that there is nothing one can do on the PCB to correct a bad IC
package(s).
I agree that misreferencing is a common problem, and DET does not address
that, nor should one try.
Two wrongs may not make a right but three do! ( I felt I had to throw that
in. )
I don't advocate small caps either, unless there is a very specific
frequency that a tuned filter can address. Using small capacitors in the
same case size that supports larger values just increases the number of
parts and cost.
However, a point at which we diverge seems to be how much noise escapes the
board due to repeated reflections impinging vias and escaping through
features / components on the board exterior.
Regards,
Steve.
At 05:14 PM 12/6/2004 -0800, Chris Cheng wrote:
>Steve,
>There is more to consider besides economics/politics.
>One has to ask where does those EMI noise comes from in the first place. If
>the noise comes from the Si core switching, I would think it falls backs to
>my core power distribution I always repeat in the Si-list.
>You will have to
>convince me that the noise is trapped in the PCB and not the package
itself.
>If it is the later, no DET on the PCB will help.
>If the noise comes from improper referencing of I/O (like adding a
>microstrip signal layer at the bottom in case 6) you will have a helluva
>problem at hand besides the edge radiation issue. Which brings back my
>argument of two wrong does not equal to one right.
>My suspicion comes from this is the 4th or 5th platforms I have designed
>where I deliverately not put ANY decoupling capacitors smaller than 1nf on
>the PCB other than for specific analog PLL or circuit fitler requirement. I
>just don't believe there will be excessive >100MHz noise trapped in the PCB
>if your manage your I/O return path and package decoupling properly.
>If it isn't there, why do you need to fix it ?
>
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