[SI-LIST] Re: Why is capacitor with high ESR
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'''Si-List ' ' '" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 6 Dec 2004 17:14:52 -0800
Steve,
There is more to consider besides economics/politics.
One has to ask where does those EMI noise comes from in the first place. If
the noise comes from the Si core switching, I would think it falls backs to
my core power distribution I always repeat in the Si-list. You will have to
convince me that the noise is trapped in the PCB and not the package itself.
If it is the later, no DET on the PCB will help.
If the noise comes from improper referencing of I/O (like adding a
microstrip signal layer at the bottom in case 6) you will have a helluva
problem at hand besides the edge radiation issue. Which brings back my
argument of two wrong does not equal to one right.
My suspicion comes from this is the 4th or 5th platforms I have designed
where I deliverately not put ANY decoupling capacitors smaller than 1nf on
the PCB other than for specific analog PLL or circuit fitler requirement. I
just don't believe there will be excessive >100MHz noise trapped in the PCB
if your manage your I/O return path and package decoupling properly.
If it isn't there, why do you need to fix it ?
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Monday, December 06, 2004 2:40 PM
To: Chris Cheng; '''sguzek@xxxxxxxxx ' ' '; '''Si-List ' ' '
Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
Chris, I agree that the cost factor that you point-out is a big issue that
may well never get solved. I just don't see DET making it to the
mainstream market. But the economic and political issues are separate from
the technical issues. I am not holding my breath. I will be pleasantly
surprised if high ESR caps do become widely and cheaply available.
Minimizing noise energy is always a good idea.
Regards,
Steve
At 01:59 PM 12/6/2004 -0800, Chris Cheng wrote:
>I am sure some workstation/server company will ship their AMD volume
>products with lot's o DET cap to compete with the Taiwan/China no name
brand
>PCB that will actually take away passives until it fails FCC and then put
>the last one they remove back to squeeze thru FCC. Then again, what do I
>know. I just design servers.
>
>And there will always be fools like me who will stick with structures like
>7) and thinking their feraday cage is good enough to contain the noise.
>
>Finally, I also believe minimizing the noise energy is the first thing you
>should do. Following my simple rules of managing the I/O return paths and
>stage your core power distribution through die/package/pcb and you will
need
>less of those cages or dissipation.
>
>It's like buying your teenage kid a drum set and then trying to figure out
>how to sound proof your room and house. Don't get the drum set in the first
>place.
>
>-----Original Message-----
>From: steve weir [mailto:weirsp@xxxxxxxxxx]
>Sent: Monday, December 06, 2004 12:41 PM
>To: Chris Cheng; Chris Cheng; Chris Cheng; Chris Cheng;
>'''sguzek@xxxxxxxxx ' ' '; '''Si-List ' ' '
>Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
>
>
>Chris, I see two separate threads:
>
>1. Does DET work?
>2. Is DET technically and economically practical.
>
>I have a hard time seeing DET becoming practical due to human
>nature. Istvan disagrees with me, but the problem that I see is that DET
>caps are very specialized so it will be really hard to convince a mfg to
>make them unless there is both strong customer demand, and customer demand
>at a premium over ordinary caps. At the same time, OEMs will be very
>hesitant to do something new especially if it involves risk in the supply
>chain and "expensive" commodity items. I would like Istvan's vision to
>work-out, but I don't see it happening. That might change if some really
>big OEMs decide that they want to demand high ESR caps from their
suppliers.
>
>As to DET working? Istvan is probably the most prominent individual
>carrying the banner for DET with a number of papers and a whole lot of
>invested effort, but he is not alone. Patents by Hitachi back in the mid
>1990s address damping planes for among other reasons EMI reduction.
>
>Now, let's look at the thought problem that you propose: TIG welding shut
>one side of a cavity, versus placing a lossy load across the
>aperture. Although it may not be intuitively obvious, in the perfect case
>for each, no energy escapes. The difference between the two is that with
>the DET case, the energy has been dissipated. In the TIG welded case, the
>energy has simply been reflected and is still available to escape somewhere
>else, and that from an EMI perspective is the problem that DET sets out to
>address.
>
>Personally, I like TIG welds. If I could find a TIG weld that supports DC
>I would have a really good decoupling capacitor.
>
>Regards,
>
>
>Steve.
>At 12:10 PM 12/6/2004 -0800, Chris Cheng wrote:
> >I have a hard time getting through the thought experiment.
> >I you have a computer chassis with solid ground and you cut it in half
and
> >isolate one half and tie it to power. You then connect the to halfs by
your
> >DET caps, do you think the EMI performance will be better than spot
> >soldering the two halfs together and maintaining both at ground ?
Remember,
> >spot soldering is almost free and I can always put more solder joints
than
> >DET caps.
> >
> >-----Original Message-----
> >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> >Sent: Monday, December 06, 2004 11:18 AM
> >To: Chris Cheng; Chris Cheng; Chris Cheng; '''sguzek@xxxxxxxxx ' ' ';
> >'''Si-List ' ' '
> >Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
> >
> >
> >Chrsi no problem, we'll take care of that noise with single points and
> >splits! Seriously, if you would like to do a test vehicle out of
academic
> >interest, I think you will find that DET does a better job suppressing
EMI
> >than a highly reflective fence.
> >
> >Regards,
> >
> >
> >Steve
> >At 10:48 AM 12/6/2004 -0800, Chris Cheng wrote:
> > >The reality will be the top/bottom layers will have microstrip signals
> >added
> > >(8 layers) which will force me to use ground plane reference and
> >arrangement
> > >like 6) with outer signal layers added will unlikely to happen in my
> >design.
> > >If you have microstrip signals and construct it with power as reference
> > >plane at the bottom as in 6). You are in for more trouble than edge
> > >radiation.
> > >
> > >-----Original Message-----
> > >From: steve weir
> > >To: Chris Cheng; Chris Cheng; ''sguzek@xxxxxxxxx ' '; ''Si-List ' '
> > >Sent: 12/6/2004 10:38 AM
> > >Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
> > >
> > >Chris, I agree that 7 will work better than 5, although it might be a
> > >little bit less representative of what people actually build.
> > >
> > >Where we disagree is whether 7 will actually be better than 6. I don't
> > >think it will for the reasons stated. Do you think you can convince
> > >your
> > >company to build two test boards, one as 7 and one as 6? The
> > >alternative
> > >is to run models, assuming we want to trust them.
> > >
> > >Regards,
> > >
> > >
> > >Steve
> > >
> > >
> > >At 10:12 AM 12/6/2004 -0800, Chris Cheng wrote:
> > > >Steve,
> > > >I would think
> > > >
> > > >7)
> > > >Gnd
> > > >Power
> > > >Signal
> > > >Signal
> > > >Gnd
> > > >Gnd
> > > >
> > > >with the fence and sea of vias and decoupling in between will be
better
> > >than
> > > >6)
> > > >
> > > >For 4) it is obvious there is no edge containment.
> > > >For 5) while the edge containment can help the first five layers, the
> > >bottom
> > > >power plane can still have noise current which solely relie on
> > >decoupling
> > > >caps that may or may not be effective and you will need a case like
6)
> > >to
> > > >ensure the complete edge containment (since you can short the
gnd/power
> > > >planes with vias).
> > > >
> > > >-----Original Message-----
> > > >From: steve weir
> > > >To: Chris Cheng; 'sguzek@xxxxxxxxx '; 'Si-List '
> > > >Sent: 12/5/2004 11:30 PM
> > > >Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
> > > >
> > > >Chris,
> > > >
> > > >No, I don't see a lot of value from the very low R's in existing
> > > >caps. Yes, lots of ground vias do divide the cavities up and cause a
> > > >lot
> > > >of scattering. Unfortunately, even a good number of those vias rise
to
> > > >the
> > > >surface to meet decoupling caps which then become a source of
> > > >radiation. This is not to mention the other signal vias that do the
> > > >same
> > > >thing.
> > > >
> > > >We could have some fun constructing some ML boards with a stackup
> > >having
> > > >at
> > > >least two ground planes one close to each end of the stack-up that
> > > >allows
> > > >for a fence. We could add more layers, but I think the following 6
> > > >layer
> > > >is adequate for the thought-problem / experiment:
> > > >
> > > >Gnd
> > > >Power
> > > >Signal
> > > >Signal
> > > >Gnd
> > > >Power
> > > >
> > > >1. Oscillator with nice fast CMOS drivers in the middle as our noise
> > > >source, aside from local decoupling in the middle of the board, it
will
> > > >be
> > > >an open cavity.
> > > >2. Same as 1. but with ground fence only at the board edges.
> > > >3. Same as 1. but with fence using DET with the best dissipative
caps
> > > >that
> > > >we can get.
> > > >4. Same as 1, but with lots of ground and power vias distributed
> > > >around
> > > >the board many connecting to decoupling caps on the surface.
> > > >5. Save as 4, but with fence as in 2.
> > > >6. Same as 4, but with DET as in 3.
> > > >
> > > >I believe that we agree that between 1, 2, and 3, that 3 will have
the
> > > >lowest radiation.
> > > >I believe that we agree that between 1 and 4, 2 and 5, and 3 and 6,
> > > >4/5/6
> > > >will have lower radiation than 1/2/3 respectively.
> > > >
> > > >What I think you will find interesting is that of 4, 5, and 6, that 6
> > > >offers considerable improvement over both 4 and 5. This has been the
> > > >subject of much of Istvan's work on the benefits of DET. The
impinging
> > > >energy only hits the vias once on its way out to the board edge where
> > >it
> > > >is
> > > >absorbed. The "ice-cube trays" of 4. help to remove a lot of the
> > > >coherency
> > > >from the noise, but we are pretty much stuck with the dielectric
losses
> > > >to
> > > >dump the HF energy into heat. What does not become heat escapes on
its
> > > >way
> > > >to Zontar.
> > > >
> > > >I hope that we can agree that an alternative demonstration is to
break
> > > >up
> > > >the Vcc plane into sections that are tied together with lossy
> > >decoupling
> > > >
> > > >networks. Would you be surprised to find that the EMC performance of
> > > >such
> > > >a board with a thick cavity is much better than the same geometry
board
> > > >where the Vcc has not been divided, sic 1, or 4 from above?
> > > >
> > > >Regards,
> > > >
> > > >
> > > >Steve.
> > > >
> > > >
> > > >At 10:41 PM 12/5/2004 -0800, Chris Cheng wrote:
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