[SI-LIST] Re: Why does lamination fail to prevent eddy currents at high frequencies?
- From: Ray Anderson <Raymond.Anderson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 28 Mar 2002 10:36:41 -0800 (PST)
Lee Ritchey wrote:
>
>
>You bet! The capacitor formed by parallel plate capacitance is the best in you
>PCB.
>
>Lee
>
Wasn't the original poster asking about about laminated conductors
(like a laminated transformer or solenoid core) as opposed to
a laminated pcb stackup ?
I must admit that I was confused by the wording of his request,
but got the impression that he wasn't talking about pcb laminations.
If indeed he was talking about laminated cores, then even if the individual
laminations were insulated from each other by some sort of varnish
I don't think the capacitance between the laminations would effect
the eddy currents (or lack of them).
Then again, perhaps I am just confused about the original question :)
-Ray
> Steve Rogers (the original poster) wrote:
>
> > I have seen a number of simple derivations explaining why it is a good idea
> > to laminate a conductor which lies in a magnetic field. The idea being to
> > slice up the material in the direction of the flux and hence break the path
> > of eddy currents. This is all very well and good, I then find it mentioned
> > in passing that this technique fails at high frequency but have not yet
> > found a good explanation as to why?
> >
> > Would anyone care to have a stab at an explanation, or maybe poiint me in
> > the direction of one?
> >
> > Thanks in advance
> >
> > Steve
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