[SI-LIST] Re: Why Termination at Both End ?
- From: Ihsan Erdin <erdinih@xxxxxxxxx>
- To: alfred1520list <alfred1520list@xxxxxxxxx>
- Date: Thu, 25 Aug 2011 00:16:05 -0400
Alfred,
The RF theory explanation to this seemingly mysterious phenomenon doesn't
sound convincing to me for two reasons. First, how is it possible that the
far end open circuit is transformed to a near end short circuit while the
near end is already terminated by a resistor? Second, if it were really
transformed to a short then you should have observed zero volt not the
average dc voltage which is half the clock voltage swing. The only plausible
explanation is that the average dc voltage must be the result of the
matching or almost matching near end termination-line impedance relation.
In this case the answer has more to do with the transmission line reflection
theory than the standing wave theory you brought about. Let's test this
argument with the numbers. Your clock has a period of about 6ns. With a 50%
duty cycle its bit time (i.e. high/low logic time) will be 3ns. But this is
pretty much the two way prop delay for a 10" long PCB trace on FR4. When
your pulse reached the receiver side it doubled in amplitude (reflection
from open) and started to travel back to the terminated near end. Its
arrival at the near end after 3ns coincided with the following logic low
sunk by the driver. So when you probed it at the near end termination what
you really observed was nothing but a series of back-to-back high pulses;
alternating between the original signal from the driver and the far end
reflection, with the latter simply filling in the original logic low time.
To an unsuspecting eye this whole phenomenon should look like dc at about
half the voltage swing with possible glitches at the logic transition times
(i.e. rising/falling edges) that will look like noise.
I personally didn't try this in the lab nor simulated it. This is nothing
but a gedanken experiment which can be easily put to test by a 5-10 line
long spice netlist. If the good old reflection theory is correct I bet
you'll observe what I describe here with this interesting coincidence
between the electrical line length and the clock period.
Should we worry about the receiver then? No, because the reflected wave will
be absorbed by the near end (matching) load and the receiver will not
experience this bizarre dc-looking waveform, hence no problem there. Thus,
with properly terminated lines one doesn't need to worry about the line
electrical length and wavelength ratios in the constraint settings. As
usual, most of our concerns for long lines should come from the less sexy
copper/dielectric losses at high frequencies.
Regards.
Ihsan
On Wed, Aug 24, 2011 at 12:40 PM, alfred1520list
<alfred1520list@xxxxxxxxx>wrote:
> ----- Original Message -----
> From: <Peter.Pupalaikis@xxxxxxxxxx>
> Sent: Wednesday, August 24, 2011 12:03 AM
>
> > Steve's comments reminded me of a situation we were discussing about a
> chip
> > design the other day. That is, if you do have an imperfect (or purposely
> > bad) termination at the receiver end (like a high-impedance), then try
> not
> > to evaluate any performance by looking at the waveform at the source - it
> > may look horrible and in the case of a clock, it is possible that the
> > voltage waveform is nearly non-existent, while the waveform at the
> receive
> > end looks fine.
>
> I can attest to this. It happened on a pretty mundane situation. I
> thought I'll
> share so some one like myself a few years ago would benefit.
>
> We have a 148.5 MHz video clock driving a relatively long trace, around 10"
> long,
> that's in the inner layer. As usual we only source series terminate it.
> So when
> we have some video problems, we look at the clock line. Since we don't
> have
> easy access to the end of the line, we looked at the down stream side of
> the series termination resistor, THERE IS NO CLOCK, just a
> constant DC line with a little
> bit of noise. How could it have ever worked? After some series head
> scratching
> and pondering, we realized this is exactly the situation that Peter
> described.
>
> Looking from the RF antenna engineering point of view, this should be
> obvious. When the transmission line is exactly 1/4 the wave length, it
> becomes
> a 1/4 wave transformer that transforms the open circuit at the far end to a
> short
> at the near end, hence the flat line. DC is not affected by the
> transformer so you
> see only the DC average of the waveform.
>
>
> Best Regards,
> Alfred Lee
>
> http://www.mds.com
>
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--
Ihsan Erdin
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