[SI-LIST] Re: Why SSTL_2 does not need 1_25V Pull Up in AGP card ?

  • From: Mike Brown <bmgman@xxxxxxxxxx>
  • To: chris.mcgrath@xxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Sun, 13 Oct 2002 21:04:36 -0500

Chris's remarks about reduced swing being an EMI benefit are certainly 
true.  The reduced swing and fast signalling are a result of the 
termination of the net accomplished by the "pull-up" resistor.

The SSTL2 driver is a "totem pole" structure (A P-channel and N-channel 
FET in series between VDDQ and VSS.)  As such, it needs no "pull-up" to 
establish a valid voltage level in either state. The driver swings 
rail-to-rail under light loading, and beyond the rails with unterminated 
transmission line loads. The so-called "pull-up" to VDDQ/2 is a 
termination resistor, of 50 ohms more or less, presumably at one end 
(Class 1, 8 ma driver) or both ends (Class 2, 16 ma driver) of the 
interconnection trace.  The resistor consumes DC power in both states 
and is considerably more power-hungry than a series-terminated net would 
be.  There is a minimum of  8 (or 16) ma of current flowing all the 
time, rather than just for the round-trip time of the interconnect.   
Note that a 1.25v termination supply must both source and sink current. 
 Thevenin equivalent termination (100 ohms to VDDQ, 100 ohms to VSS) 
does not have this issue, at the expense of higher power consumption 
from the 2.5 volt supply.

Series termination also works with SSTL2, if you are concerned with the 
power and can stand the time delay imposed by full-swing transitions and 
the mid-swing porch on multi-drop nets. (Don't do this with a clock 
net!)  Other termination topologies are possible with SSTL2, within the 
8 (or 16) ma Ioh and Iol specs of the driver.  SPICE  is probably needed 
to prove the viability of anything other than a conventional topology.

The Vref in SSTL2 is a receiver threshold control and has almost nothing 
to do with the 1.25 volt termination voltage other than VDDQ/2 being 
near the "ideal" threshold value to minimize duty cycle distortion.  DCD 
is of great concern with DDR-clocked devices.

Regards

Mike

chris.mcgrath@xxxxxxxx wrote:

>SSTL2 isn't really "pulled up" to 1.25V.  More accurately, this is the
>reference voltage (often referred to in data sheets as VREF) that the
>signals swing around.  This bias allows for less voltage swing and this
>translates into a better EMI picture since the edge rates are slower yet can
>still achieve the same data transfer speeds.  One would also expect that
>less power is required since the signals are not banging between the rails.
>
>-Chris
>
>
>  
>
>>-----Original Message-----
>>From: Jack W.C. Lin [mailto:JackWCLin@xxxxxxxxxxxx]
>>Sent: Thursday, October 10, 2002 10:54 PM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Why SSTL_2 does not need 1_25V Pull Up in 
>>AGP card? 
>>
>>
>>Hi All SI friends:
>>We all  know that in SSTL_2 spec, DDR signals need 1_25V pull 
>>up. But I
>>found one thing in recently job for AGP 8X card simulation, 
>>all DDR signals
>>need not 1_25V pull up! SSTL_2 input receiver is differential input
>>receiver, the signal should swing above/below on 1_25V. Why 
>>does it still
>>can work properly?
>>Anyone provide reasonable explanation? Thanks
>>Jack   
>>
>>
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