[SI-LIST] Why DDR needs larger impedance when during WRITE operation?

  • From: "jinfeng@xxxxxxxxx" <jinfeng@xxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 20 May 2014 00:29:32 +0800

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  • » [SI-LIST] Why DDR needs larger impedance when during WRITE operation? - jinfeng@xxxxxxxxx
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