[SI-LIST] Re: Where is the Return Current when signal transition from GND reference to POWER reference
- From: Tesla <emcesd@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 1 Mar 2012 09:33:25 +0800 (CST)
Hi, experts
Thank you all of you!
Best Regards.
Tesla.
At 2012-03-01 01:23:13,"Oh, Dan" <doh@xxxxxxxxxx> wrote:
>Hi Tesla,
>
>In addition to Eric's paper, I have also written a paper on this subject and
>published in IEEE last year:
>D. Oh, "Plane bounce in high-speed single-ended signaling systems," DesignCon
>2012.
>If you have access to DesignCon, I also wrote a paper with little more details
>this year:
>D. Oh, "Plane bounce in high-speed single-ended signaling I/O interfaces,"
>EPEPS conference 2011.
>Please let me know if you do not have access for any of these. I can forward
>to you.
>
>Best,
>- Dan Oh
>___________________________________________
>Dan (KyungSuk) Oh, Ph.D.
>Technical Director of Signal and Power Integrity
>Rambus Inc.
>(B) 408-462-8363
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Bill Martin
>Sent: Wednesday, February 29, 2012 5:08 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Where is the Return Current when signal transition from
>GND reference to POWER reference
>
>Tesla,
>
>Eric Bogatin has published some analysis on a similar design in his Blog.
>
>It was posted Sept 2010 concerning Cross Talk in Differential Channels (return
>path discontinuities).
>
>Location: http://bethesignal.net/blog/?m=201009
>
>Regards,
>Bill
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Tesla
>Sent: Wednesday, February 29, 2012 2:51 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Where is the Return Current when signal transition from GND
>reference to POWER reference
>
>Hi, experts
>
>I have a question that buffled me a long time.
>
>Suppose i have a four layers board. L1:TOP L2:GND L3:POWER L4:Bottom (GND
>and POWER are ground plane and Power plane), there are not any connections
>between L2:GND and L3:POWER. they are independant planes. there is not even a
>capacitor between them.
>If I have a 200mils signal trace run on L1: TOP, Then it transition to
>L4:Bottom layer through a through hole via. The signal trace also run 200mils
>on L4:Bottom. I design the Signal trace as 50ohm.
>Now, if i launch AC signal into signal trace on L1:Top layer. Would i
>mearsure signal between L4:Bottom and L3:POWER at the end of signal trace.
>I believed that there is not voltage between the trace and POWER Plane,
>because the return current can't find a way to transition to L3:POWER.
>But when i simulated the case in HFSS. I get a result that it has S-parameter
>like a 400 mils microstrip from DC to 1Ghz.
>which is correct?
>Hope such silly question not bother you.
>
>Thanks.
>
>Tesla.
>
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