[SI-LIST] What should be checked on ASIC
- From: Bob Patel <whizplayer@xxxxxxxxx>
- To: si_list <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Mar 2002 09:21:44 -0800 (PST)
Hi!
I am trying to get feedback on
a) What are the different simulation exercises
b) What levels of testing can be done
These questions pertain to an ASIC chip which will be
running at 2.5GB/s and the rise /fall times can be as
low as 50pS on the output.
With such rise & fall times the package itself behaves
as a transmission line and there are steps to be
taken such that Signal Integrity of the signal at the
pad is not compromised. Also issues like ground
bounce, power droops have to be taken into account.
In a fabless company we cannot rely on the ASIC FAB
vendor to deliver a chip which has gone through these
levels of testing because the FAB vendors are either
new or it takes up too much time for them.
On our part if i had to do due diligence, what are the
differnt SI issues to be taken care off.
I would like any consulting service who offer such
service and work with FAB vendors or a fabless company
which has gone through thsi exercise on a chip working
with fast rise/fall times.
Any input on/off the list will be appreciated.
Thanks in advance.
Bob
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