[SI-LIST] Re: What is the difference between tDQSS, tDSS and tDSH
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>, Istvan Nagy <buenos@xxxxxxxxxxx>
- Date: Mon, 29 Mar 2010 09:51:37 +0200
Hi Istvan,
I did not check the Spec yesterday and I have to admit, that I was only
thinking about tDS and tDH, not about tDSS and tDSH.
As you mentioned already: tDQSS is defining the rising DQS edge, while
tDSS/tDSH are definitions for the falling DQS edge.
The main reason, why I have not thought about the tDSS is, that the
designs that I knew did not care about the falling DQS edge, but
generated this timing information internally.
Basically this is to avoid any issues on duty cycle distortion.
This is really one thing where several conditions would need to be
fulfilled and not all configurations are possible due to some other
restrictions in the spec.
If you run at tDQSS min you will never have problems with tDSS, but only
with tDSH. I'm just looking at a Micron 2Gb spec, ant there is a picture
for the write burst timing.
In this picture are the 3 cases tDQSS min / nom / max shown. For "tDQSS
min" only tDSH is shown.
in the case for "tDQSS nom" both tDSS and tDSH are shown and in the case
for "tDQSS max" only tDSS is shown.
Basically this means you are not allowed to run the system at tDQSS min
with a tDQSH duty cycle of 0.55, as you would violate tDSH in this case!
In the picture in the JEDEC spec (page 69) there are all tDSS and tDSH
values shown, but as you see there are some very long times that will
never violate the min value.
What is a bit strange to me in the moment are the numbers for the
different speedgrades:
For tDQSS the 3 lower speedgrades show +- 0.25tck while the DDR3-1600
shows +-0.27tck while the numbers for tDSS are 0.2 tck for the lower
speedgrades and 0.18 for the DDR3-1600.
I don't remember why this is going into different directions...
Sorry for not checking the spec before answering...
regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 / 902 083
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sorry, it was wrong:
instead of:
"is it possible that DQSCK is for DQS-rising-to-CLK-rising edge timing,
while DSS/DSH are for DQS-falling-CLK-rising edge?"
i meant:
"is it possible that DQSS is for DQS-rising-to-CLK-rising edge timing,
while DSS/DSH are for DQS-falling-CLK-rising edge?"
regards
Istvan Nagy
schrieb steve weir:
> Istvan, refer to Figure 40- Write Timing Parameters. Note that the
> timing reference lines for tDS, tDSS, and tDSH are to DQSdiff, while the
> reference lines for tDQSS and tDQSH are to CKdiff.
>
> Steve
> Istvan Nagy wrote:
>
>> Hi
>>
>> Thanks for the answer.
>> I think t_DSS and t_DSH are not DQ-to-DQS timings.
>> JESD79xx says t_DS and t_DH are DQ-to-DQS timings, but they say
>> t_DSS/t_DSH are : " DQS falling edge to CK setup time".
>> is it possible that DQSCK is for DQS-rising-to-CLK-rising edge timing, while
>> DSS/DSH are for DQS-falling-CLK-rising edge?
>>
>> regards,
>> Istvan
>>
>> ----- Original Message -----
>> From: "Hermann Ruckerbauer" <hermann.ruckerbauer@xxxxxxxxxxxxx>
>> To: "Istvan Nagy" <buenos@xxxxxxxxxxx>
>> Cc: <si-list@xxxxxxxxxxxxx>
>> Sent: Sunday, March 28, 2010 8:50 PM
>> Subject: [SI-LIST] Re: What is the difference between tDQSS, tDSS and tDSH
>>
>>
>>
>>
>>> Hi Istvan,
>>> t_DQSS is an input parameter to align DQS to clock input. As you
>>> mentioned, this is basically to make sure that the DRAM is activating
>>> it's receiver at the right time to catch the preamble of the DQS.
>>>
>>> tDSS and tDSH are just the normal Setup/Hold times that every receiver
>>> needs. In this case it is the relation of the DQ to the corresponding
>>> timing signal, the DQS, so they are pure input timings.
>>>
>>> In the DRAM spec there are several cases that two different timings need
>>> to be fullfilled, but sometimes it is not possible that all combinations
>>> are valid. I would need to check the exact timings, but I guess this is
>>> one of this cases.
>>>
>>> Setup time is always minimum required input setup time, and as you
>>> mentioned "at a given point on the board": All timings are defined at
>>> the ball of the DRAM.
>>>
>>>
>>> Regards
>>>
>>> Hermann
>>>
>>>
>>>
>>> EKH - EyeKnowHow
>>> Hermann Ruckerbauer
>>> www.EyeKnowHow.de
>>> Hermann.Ruckerbauer@xxxxxxxxxxxxx
>>> Veilchenstrasse 1
>>> 94554 Moos
>>> Tel.: +49 (0)9938 / 902 083
>>> Mobile: +49 (0)176 / 787 787 77
>>> Fax: +49 (0)3212 / 121 9008
>>>
>>>
>>> schrieb Istvan Nagy:
>>>
>>>
>>>> Hi
>>>>
>>>> The JESD79-xx Jedec standards specify three timing parameters for DDRx
>>>> memory write clock-strobe timing:
>>>> tDQSS, tDSS and tDSH.
>>>> I understand the t_DQSS, that it makes shure that the strobe will arrive
>>>> to
>>>> the memory chip within a window relative to the clock, so we will latch
>>>> the
>>>> right data bit at the right time.
>>>> but what is the purpose of the other two parameters?
>>>> they seem to have a tighter value, so if they specify the same write
>>>> clk-strobe matching, then the DQSS specification does not make sense,
>>>> since
>>>> the other two parameters already specified the same thing with a narrover
>>>> limit.
>>>> anyway, are the DSS and DSH parameters input requirements or output
>>>> guaranteed timings?
>>>> the jedec specs dont really make a difference between input requirements
>>>> and
>>>> output guaranteed timings in the explanations of the timing parameters.
>>>> for
>>>> example they say "setup time", but it can mean "input setup requirement"
>>>> or
>>>> "output worst-case guaranteed setup time", or just the actual setup time
>>>> of
>>>> a signal on a given point on the board.
>>>>
>>>> regards,
>>>> Istvan Nagy
>>>> CCT
>>>>
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