[SI-LIST] What is the difference between tDQSS, tDSS and tDSH
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sun, 28 Mar 2010 15:17:46 +0100
Hi
The JESD79-xx Jedec standards specify three timing parameters for DDRx
memory write clock-strobe timing:
tDQSS, tDSS and tDSH.
I understand the t_DQSS, that it makes shure that the strobe will arrive to
the memory chip within a window relative to the clock, so we will latch the
right data bit at the right time.
but what is the purpose of the other two parameters?
they seem to have a tighter value, so if they specify the same write
clk-strobe matching, then the DQSS specification does not make sense, since
the other two parameters already specified the same thing with a narrover
limit.
anyway, are the DSS and DSH parameters input requirements or output
guaranteed timings?
the jedec specs dont really make a difference between input requirements and
output guaranteed timings in the explanations of the timing parameters. for
example they say "setup time", but it can mean "input setup requirement" or
"output worst-case guaranteed setup time", or just the actual setup time of
a signal on a given point on the board.
regards,
Istvan Nagy
CCT
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
