Hi Kia, I can't answer your question about the probability distribution for when a device will switch. I don't think any one but the manufacturer of the device could provide this information. It would seem that every different device would have the potential to have a different switch probability "signature" though, depending on process technology, among other things... I will say that in many cases the manufacturer will specify that the flight time to the input switching threshold (typically VDD/2 but please see the specs to find this value and if it is applicable) can be used as long as the input slew-rate requirements are met. Otherwise, your methodology would be required. It would seem that measuring to VinH/VinL could be overly conservative if slew-rate requirements are being met, hence you could have the potential for many false "negative margin" cases. (Is that a double negative :-) oops. While this doesn't answer your specific question, I thought I would at least share this, since, in my mind, it seems pertinent... Sorry if it isn't. Best regards, Steve Stephen P. Zinck Interconnect Engineering 25 Bennett Lot Road South Berwick, ME 03908 Phone - (207) 384-8280 Fax - (207) 384-5388 Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx Web - www.interconnectengineering.com ----- Original Message ----- From: "Kai Keskinen" <kalevi@xxxxxxxxxx> To: <si-list@xxxxxxxxxxxxx> Sent: Tuesday, March 01, 2005 4:49 PM Subject: [SI-LIST] What is probability distribution for logic switching >A little question about probability here: > > When we do static timing analysis (STA) using simulation tools, we extract > the flight times with buffer delay compensation for a rising edge with > the > minimum time being when the signal goes through VinL and the maximum time > being when the signal goes through VinH. Does anyone know what kind of > probability distribution there is for when the device actually switches? > Let's assume we are taking about CMOS and use a rising edge as an example. > Assume no noise or cross-talk, just a nice quiet receiver getting a nice > clean edge. > > Does anyone have a good reference for doing statistical timing analysis? > What I mean is calculating the likelyhood of a timing failure occurring if > the STA has shown a negative margin. With the faster clock speeds, we are > getting more negative margins with one or more corner cases and sometimes, > there appears to be no reasonable fix to get positive timing for all > cases. > > Any suggestions will be greatly appreciated. > > Kai > > > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > List FAQ wiki page is located at: > http://si-list.org/wiki/wiki.pl?Si-List_FAQ > > List technical documents are available at: > http://www.si-list.org > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu