[SI-LIST] Webinar on chip-package co-design for power integrity

From: "Ji Zheng" <jizheng@xxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 30 Apr 2008 16:00:57 -0700

Dear colleagues, 
 

Apache Design Solutions will be hosting an educational webinar on May 8th at
11AM PDT on the topic of chip-package co-design using chip power model
(CPM).  The webinar will include a guest speaker from Cisco to share
application and results obtained by CPM in their networking system designs.

 

When: May 8th (Thursday) @ 11AM PDT

What: Technical webinar

How to Register:
http://seminar2.techonline.com/registration/wcRegForm.cgi?sessionID=apache_m
ay0808

 

Anyone doing physical designs especially at 90nm and below or signal
integrity engineers, package and system power deliver network design
engineers, and design methodology and design architects should find this
webinar useful.

 

Thanks, 

Ji

 

 

Ji Zheng

 

Apache Design Solutions

 



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[SI-LIST] Webinar on chip-package co-design for power integrity

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