[SI-LIST] Voltage levels of DDR2 simulation in Hyperlynx

From: Allan Wang <allanw@xxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Mon, 7 Feb 2011 18:07:24 -0500

Sorry if this is a bit basic for this mailing list. I'm trying to simulate
DDR2 terminations according to Altera's external memory interface handbook.
I can't figure out why my voltage swing is so large:
http://i.imgur.com/kCRSE.png

I believe the swing should be 0.65 - 1.15V.

Allan


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[SI-LIST] Voltage levels of DDR2 simulation in Hyperlynx

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