[SI-LIST] Re: Vias on decoupling pads (aka plugging)
- From: "Sol Tatlow" <Sol.Tatlow@xxxxxxxxxxxxxxx>
- To: "Paul Levin" <levinpa@xxxxxxxxxxxxx>,"SI-List Reflector" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 6 Apr 2004 18:05:14 +0200
Hmmm .... plugging .... well, there are lots of different
kinds, including: take a look at
http://www.chipit.de/ce/CHIPitPlatinumEdition.htm#
to see one of the several types of products (ASIC verification)
I am involved in (featuring 25,000 pin boards with 18 layers,
where I am proud to say, ONLY 18!) - PCB design, product
packaging, 3D virtual modelling and certification were my main
domains with this product.
Apart from cheap self-promotion ;-), plugging (of the PCB
kind) is a whole specialist area in itself, which can be
used for one or more of several purposes:
1. filling of normal through hole vias to allow a board
to be tested on a vacuum ICT machine;
2. filling of micro-vias to provide a flat solderable
surface (via-in-pad) for BGAs (or in this case, decoups -
Vincenzo, it has nothing to do with the PCB fab house,=20
rather the ASSEMBLY guys, where the SOLDER PASTE will
otherwise disappear into the hole =3D no joint!);
3. filling of blind and buried vias to prevent manufacturing
defaults (exploding vias during soldering, long-term
after-etch problems, etc).
Materials used vary from non-conductive resin compounds to
conductive silver compounds, 'solid' or liquid - what type of
compound used will depend upon the cost/volume/purpose
combination: an interesting, almost side-effect of conductive
plugging can be the reduction of resistance/impedance of a=20
through board connection - although at high frequencies the
skin effect reduces this 'handy' effect, this still has uses
in heat transfer (from one side of PCB to other) and in
relatively low frequency/high current areas like switch mode
PSUs.
Processes used to be mainly screen or stencil but there are
now others such as Roller Coating that enable relatively high
PCB-thickness-to-hole-diameter aspect ratios (>15), as well as
much more reliable internal (buried) via plugging.
In general though, plugging used in combination with micro,
blind and buried vias always increases complexity and
price of a board, and is therefore usually reserved for
really high density designs, but it can mean a reduction
in the number of layers used, which in boards with high
layer counts might make the difference between possible and
impossible - typical applications include boards with high
density BGAs on one side, and fine pitch high density SMD
connectors (like the 'BGA' types available from SAMTEC - an
utterly brilliant connctor company) on the other. In some
cases you can also expect performance bonuses.
A good start point for microvias:
http://www.circuitree.com/CT/FILES/HTML/PDF/how-to-get-started-HDI.pdf
and one for plugging:
http://pcdandm.com/pcdmag/mag/0403/0403kramer.pdf
One last thought: while such via and plugging techniques can
enable a great PCB Layouter to work wonders, without that great
PCB Layouter (MUST get into the habit of saying PCB Designer!),
and I DO mean PCB Layouter, NOT auto-router (!!!) to decide when/
if/how to use them, they will only increase your costs and give
you some major headaches!
Happy plugging ;-) !!
___________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
___________________________________
-----Urspr=FCngliche Nachricht-----
Von: Paul Levin [mailto:levinpa@xxxxxxxxxxxxx]=20
Gesendet: Dienstag, 6. April 2004 15:33
An: Sol Tatlow; SI-List Reflector
Betreff: [SPAM] - Re: [SI-LIST] AW: Vias on decoupling pads - Email =
found in subject
Dear Sol,
I would definitely like to hear more about plugging.
I bet others would too, so please post any further
thoughts and/or information on the entire reflector.
Thanks.
Regards,
Paul
_______________________
Sol Tatlow wrote:
> Hi Chris,
>=20
>=20
>>Is it ok to put vias actually on the pads of
>>a ceramic decoupling cap in terms of manufacture?
>>Do other people do this?
>=20
>=20
> yes, you CAN do this, BUT it can require technologies
> (micro-via or via-plugging techniques) that are
> otherwise not needed - this can make the PCB more
> expensive, as well as extending delivery times, plus
> can limit your choice of PCB manufacturers: it is NOT
> simply a case of placing normal vias in pads at the
> layout stage and end of story (solder paste disappears
> into the holes=3D3Dbad/no joints, solder paste application
> difficulties on other side, etc.).
>=20
> Obviously, via-in-pad CAN give you the best technical
> result/performance with very small decoupling caps,
> where there is no space to put the vias for the
> individual pads BETWEEN the pads (0603 and smaller),
> and in the case of micro-vias allows the placement
> of caps directly under full matrix BGAs where it might
> otherwise not be possible (good against 'bounce'),
> but needs to be weighed against cost requirements.
>=20
> On a more detailed level, before you use something like
> micro-vias, you perhaps also need to do analysis
> (comparison) of the impedances of the various
> possibilities of connecting the pads to the planes,
> since micro-vias are (obviously!) small. Plus, micro-
> vias (normally) only connect between neighbouring
> layers - stacking is possible, but EXPENSIVE! - which
> means they are perhaps ok for GND (L1-L2) but not
> for PWR (L1-Lx).
>=20
> Plugging is yet another different story, with different
> methods and (plugging) materials.
>=20
> If you want more info, let me know, and I can give
> you more info on manfg. techniques that will help
> you evaluate the pros and cons.
>=20
> Hope this helps!
> ____________________________________
> Sol Tatlow, M.Eng. (Oxon)
> ProDesign Electronic & CAD Layout GmbH
> Product Developer
> Albert-Mayer-Str. 16
> D-83052 Bruckmuehl
> Phone: +49 (0) 8062-808-302
> Fax: +49 (0) 8062-808-333
> Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
> www.prodesign-europe.com
> ____________________________________=3D20
>=20
> -----Urspr=3DFCngliche Nachricht-----
> Von: Chris Chalmers [mailto:cchalmers@xxxxxxxxxxx]=3D20
> Gesendet: Dienstag, 6. April 2004 12:48
> An: si-list@xxxxxxxxxxxxx
> Betreff: [SI-LIST] Vias on decoupling pads
>=20
>=20
>=20
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Paul Levin
Senior Principal Engineer
Xyratex Storage Systems
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