Hi Eric and the group,
Great example and close in many features to a homemade board I use in
my seminars. In my case also, the plane to plane voltage at 280 MHz was
about 15% of the applied signal voltage to a test path with a
plane-to-plane via just 5 mm away from a signal via penetrating the
planes!
Doug
On Wed, 6 Jul 2016 11:52:26 -0600, Eric Bogatin <eric@xxxxxxxxxxxxxxx> wrote:
Hi guys-
I'd like to echo Istvan's comment about always doing what you can that is
free, even if it has just a marginal benefit, and offer an example of why
you should worry about radiation from the edge of a board with an old war
story.
Many years ago, in my consulting days, I worked with a PC company that was
having problems getting a new product to pass part 15 class B. The first
prototype worked great. But the first production product failed.
Comparing the two units, we quickly traced the problem back to the harmonic
convergence of four problems:
1. the motherboard was 12 inches on a side. It had a lateral board 1/2 wave
resonance at about 250 MHz. The board was not designed very well, but "good
enough" to work functionally. It had a thick power and ground layer, 30 mils
thick. It had very poor decoupling. Someone in their infinite wisdom decided
to use multiple value capacitors like 1 uf, 0.1 uF and 0.01 uF without doing
any analysis and there was a parallel peak impedance resonance at around
250 MHz. Both of these were inconveniently located near the same frequency
giving a large impedance peak (about 0.5 Ohms) at around 250 MHz.
2. With the poor management of the return paths for signals, there was also
a memory bus on one the side of the board and processor on the other, which
forced many single ended signals to flow from the top of the board to the
bottom, their returns, exciting the cavity resonances. The clock was about
500 MHz, with a data rate of about 1 Gbps. Why should this cause a problem
if the dominant board resonance was at 250 MHz? Because of sub harmonics.
When the data pattern had 2 0's and 2 1's. it had a strong component at 250
MHz.
3. There was significant noise in the cavity at 250 MHz, sometimes,
depending on the various bit combinations. I would have thought the cavity
noise would have been enough to cause SI cross talk problems, but this
design escaped a bullet. However, with a thick cavity, and a 1/2 wave
resonance being excited, there was significant voltage noise at the edge of
the cavity, in the near field. The cavity noise was about 0.3v- not enough
to cause a noticeable bit failure that was fatal, but enough to generate
external field lines around the edge of the board. This was near field, and
dropped off pretty fast, so by itself, did not cause EMI failures, and the
board was, after all, in a metal enclosure.
4. However, there were cables, like DC power cables, routed inside the box
and some of these cables passed along the edge of the board. In the
prototype, the cables were very neatly tied to the inside of the enclosure
to be kept out of the way of the board so it could be snapped in and out and
replaced easily. In the production unit, the board was used to anchor some
of the cables, like the power lines. Some of the near field from the edge of
the board, at 250 MHz, coupled to the power cables and came out the DC power
cable to the external brick as common current. How much common current does
it take to fail an FCC part 15 class B test? How much common voltage coupled
on the line does it take to drive this? Not much. (I'm going to write these
answers up for my next round of rules of thumb column -
http://www.edn.com/collections/4435129/Bogatin-s-Rules-of-Thumb ;).
Bottom line, there was enough common current, induced from the near
field
from the edge of the board to fail FCC test. If the board was designed to
have lower peak impedance at 250 MHz in the cavity, if the cavity was
designed thinner, if the signals were not routed from the top to the bottom
of the board, if the cables did not happen to fall along the edge of the
board, the product unit probably would have passed FCC. No guarantee some
end users micro code wouldn’t have excited another problem or multiple
problems in the board design to cause a functional bit failure. It’s the
same effect of why tornados are attracted to trailer parks. The quick
fix, to save production, was re-route the power cables away from
the edge of the board. More robust design features were added as a longer
term fix.
The emissions from the edge of the board did not cause the failure. The near
field (capacitive) coupling to cables which happened to be routed in the box
near the edge brought the common currents outside the box to cause the FCC
failure. Is it possible for edge radiation to fail FCC? Yes, under
some conditions,
and indirectly. Do you want to assume this will happen in all boards? If
you can add a no cost design fix that will make the product robust to this
failure mode, why not? I guarantee that no one on the design team will ever
have a product fail by this mechanism again. They may have other failure
modes....
As Istvan said, if a design feature is free, and might have a marginal
benefit, why not do it? Scott McMorrow says this often- good, robust design
is one of those value added features to a product which can often be free
and add performance or reduce risk- why not take advantage of it?
I call these habits: if it's free, and may improve the performance or
reduce risk, always do it. If it costs extra, you have to evaluate the bang
for the buck. This is hard and sometimes expensive, but important for
balancing cost-performance tradeoffs. Sometimes it's like paying extra to
buy insurance.
--eric
*******************************************************
Dr. Eric Bogatin, Dean
Signal Integrity Academy
www.beTheSignal.com Adjunct Prof, ECEE Univ of Colorado, Boulder
Director, Teledyne LeCroy Front Range Signal Integrity Lab
105 S Sunset St, Suite J
Longmont, CO 80501 USA
Twitter @beTheSignal
e: eric@xxxxxxxxxxxxxxx
cell: 913-424-4333
******************************************************
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx] ;
Sent: Tuesday, July 5, 2016 11:09 PM
To: si-list digest users <ecartis@xxxxxxxxxxxxx>
Subject: si-list Digest V16 #176
si-list Digest Tue, 05 Jul 2016 Volume: 16 Issue: 176
In This Issue:
#1: From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
Subject: [SI-LIST] Re: Via fence along board edge
----------------------------------------------------------------------
Msg: #1 in digest
From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
Subject: [SI-LIST] Re: Via fence along board edge
Date: Tue, 05 Jul 2016 23:24:01 -0400
Vow! What a flurry of messages!
Yes, there is no simple conclusion in this case. EMC is the most complex
among SI, PI and EMI,
having a lot of variables, making it useless to strive for simple, generic
conclusions to cover
all situations. The basic rules are the same, but conclusions can strongly
depend on the
specifics of the application. Most of the trouble comes from structural
resonances,
whether it is SI, PI or EMI. One simple differentiator: if the signals dont
excite the
resonances, they dont cause problems. So the same structure may or may not
cause problems and need fixes depending on what are the signals on
them. Second
differentiator is if for an 'unrelated' reason we already suppressed the
structural
resonances or the PCB is in a well-shielded box where I/O connections have
low
enough common-mode signal, there will be no need for other measures to
reduce
edge leakage.
I would not worry about half-wave resonances between adjacent planes in the
stackup:
if it is a signal cavity (plane-signal-plane), we can not come close to the
half-wavelength
plane-to-plane resonance as long as we want to maintain quasi-TEM signaling.
If it is
plane-to-plane cavity with no vertical via through the cavity to excite it,
it wont be a problem.
If it is a plane-to-plane cavity with vertical vias exciting the cavity, the
vias will similarly
resonate at half wavelength and unless it is intentionally done for some
specific reason, will
cause functional failures, so the edge radiation is irrelevant.
My approach to edge stitching comes from the other extreme argument:
unless someone
shows that it makes the radiation problem worse, AND as long as it can be
implemented
without increasing cost or blocking some necessary functions, this is an
insurance policy.
The stitching vias may not decrease radiation in the particular case, or we
may not need
the stitching because we may not excite the structural resonances, or the
box shielding
takes care of it, but if it is 'free' in every aspect and it can not hurt, I
dont see a reason
why we should not use it, at least in those cases where going after all of
the details to
get a black-and-white answer would take a lot of time and resources.
Regards,
Istvan Novak
Oracle
On 7/5/2016 10:17 PM, Doug Smith wrote:
Not a simple rule for design, just one to alert me when speeds getnot > one for simple rules. As a famous person at Bell Labs said
fast enough I have to pay more attention. As you should know, I am
"Rules are > no substitute for intellegence." I would have to say
that for > simulations too.
<leeritchey@xxxxxxxxxxxxx> wrote:
Doug
On Tue, 5 Jul 2016 16:40:36 -0700, Lee Ritchey >
AH! The quest for simple rules!is >> what is important here. Just looking for a simple rule that
-----Original Message-----
From:si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Doug Smith
Sent: Tuesday, July 5, 2016 2:37 PM
To:si-list@xxxxxxxxxxxxx; Jeff Loyer<jeff.loyer@xxxxxxxxxx>
Subject: [SI-LIST] Re: Via fence along board edge
Hi Jeff,
Thanks, yes that is different. Seems like the far field radiation
will >> trigger when our designs get near a danger zone for edge
radiation.
wrote:Doug
On Tue, 5 Jul 2016 14:26:56 -0700, Jeff Loyer<jeff.loyer@xxxxxxxxxx>
wave >> guide, > > but the the dimensions are so small that theHi Doug,
You might note that Franz uses a near-field probe which will be >sensitive to a different phenomenon than what you're referring to.
Jeff Loyer[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Doug Smith
-----Original Message-----
From:si-list-bounce@xxxxxxxxxxxxx >
Sent: Tuesday, July 5, 2016 2:22 PMfrequency. > Thanks. >
To:curtmcn@xxxxxxxxx;si-list@xxxxxxxxxxxxx; LeeRitchey; Grasso, >
Charles
Subject: [SI-LIST] Re: Via fence along board edge
Hi Chas,
That seems to indicate problems well under the waveguide cutoff
DougLee > > Ritchey
On Tue, 5 Jul 2016 21:17:58 +0000, "Grasso, Charles"
<Charles.Grasso@xxxxxxxxxxxx> wrote:
Hah - at last! Simple language for the "restofus". :-)
Doug - Franz Gisins paper shows resonances well below 500GHz!!
Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t)3032042974@xxxxxxxxx
(e)charles.grasso@xxxxxxxxxxxx
(e2)chasgrasso@xxxxxxxxx
-----Original Message-----
From: Doug Smith [mailto:doug@xxxxxxxxxx] Sent: Tuesday, July 05,
2016 3:07 PM
To: Grasso, Charles;curtmcn@xxxxxxxxx;si-list@xxxxxxxxxxxxx;
want > > to show that an open side of a PCB is much like an openSubject: RE: [SI-LIST] Re: Via fence along board edge
Hi Lee,
It does not matter if the problem is made up. In this case, I
interesting >> frequencies > > are high enough as not to be a
problem. This puts the >> argument about > > PCBs into very simple
language and that satisfies >> engineering curiosity.
had >> via > > fences or > recessing to the 20h rule. So if theoverall > > principle, which is what I am getting at.Citing lots of data does not lead to an understanding of the
assumptions on the dimensions, I get frequencies over 500 GHz where >So, I think the two cases are the same and was looking for your >insight. I have done the calculations, and making reasonable > >
edge radiation as from a waveguide would happen! Just wondering ifI > > did this correctly. Doug
<leeritchey@xxxxxxxxxxxxx> wrote:On Tue, 5 Jul 2016 13:56:08 -0700, Lee Ritchey > >
imaginary > > problem. >This seems to me to be another case of trying to solve an
problem > > actually > exists before I attempt to solve it.As a side comment on my posts and the responses to them, I oftensay > that I am from Missouri, and need to be shown that a
EMI > > from > energy leaking out the edges and none of them haveIn almost 50 years of engineering and participating in the designof > more than 3000 PCBs, I have not yet seen one of them fail
problem >> really > > exists, the person > making the claim owes an
example of a >> failure > > due to the absence of > via fences.
From:si-list-bounce@xxxxxxxxxxxxx > > >There is a challenge for you! -----Original Message----- >>>>>
To:Charles.Grasso@xxxxxxxxxxxx;curtmcn@xxxxxxxxx; >[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Doug Smith
Sent: Tuesday, July 5, 2016 1:32 PM >>>>>
UC >>>> Santasi-list@xxxxxxxxxxxxx; Lee Ritchey<leeritchey@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Via fence along board edgewavelength > (at some very high
Lee, a question. If the spacing between two planes was 1/2
frequency) would not the edge of the board be a little like anfew > years. Doug
open waveguide? Probably not a practical case, at least not for
another
On Tue, 5 Jul 2016 11:39:53 -0700, Lee Ritchey ><leeritchey@xxxxxxxxxxxxx> wrote:
I think I have traced this myth to its origin. It is no more orless > than a
does > > not "leak out" the sides of a PCB to begin with. One ofmyth. >
The following papers all show with laboratory testing that EMI
them even >
shows that with or without these "grounding vias" the results arethe > same. > > > >
on > > Electromagnetic Radiation From Printed Circuit Boards",Brooks, Douglas. "90 Degree Corners, The Final Turn." PrintedCircuit > Design. January 1998
Fang, Jiayuan, et.al., "Effects of 20-H Rule and Shielding Vias
To:curtmcn@xxxxxxxxx;si-list@xxxxxxxxxxxxxon > > > > EMICruz, > Publishing date unknown. > >
Chen, Huabo, et.al., "Effects of 20H Rule and Shielding Vias
in > PCBs", UC Santa Cruz EE Department, May 2001. > >
Hope this helps. >[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Grasso, Charles
Lee Ritchey
-----Original Message-----
From:si-list-bounce@xxxxxxxxxxxxx >
Sent: Tuesday, July 5, 2016 9:21 AM >>>>>>
//www.freelists.org/archives/si-listif > > > > there will be an interference problem or not then a viaSubject: [SI-LIST] Re: Via fence along board edgedon't have a simulation tool or handy dandy formula to "guess"
If there is a concern about cavity resonances causing EMI and you
fence is > > > a
Subject > > > > >outsidegood way to sleep at night! (Just count vias instead of sheep >..one..two...three...zzzzzzz)
Best Regards[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Curt McNamara
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t)3032042974@xxxxxxxxx
(e)charles.grasso@xxxxxxxxxxxx
(e2)chasgrasso@xxxxxxxxx
-----Original Message-----
From:si-list-bounce@xxxxxxxxxxxxx >
Sent: Tuesday, July 05, 2016 6:51 AM To:si-list@xxxxxxxxxxxxxwaves
Subject: [SI-LIST] Via fence along board edge
I have seen this done, and understand the desire to trap EM >
inside the PCB. > > There are parts and short traces on the > >
layers, with ground
pours. > The next layer in is ground on both top and bottom. >
Will the ground fence always help with EMC?will > come out any opening it can find?
- Or sometimes help because that energy has to go somewhere and
- Or mostly help because those openings are small compared to thewavelength?
Curt
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