Hi Richard,
Saw your thread on Si-List, and just to clarify when introducing
new fabricators to impedance control - Polar makes it clear that coupons
for impedance may be designed for design verification - often
on the board itself - or as a one coupon per PCB or one coupon
per panel - and it is the fabs responsibility to ensure that on process
control coupons the copper coverage is similar to the board itself. Whether
on board or on panel needs to be a result of a conversation between the
board specifier and the fab - and it will depend on how critical the design
requirement is and how much space is available in the specific application.
Usually as said in the post - fabs tweak line width to control impedance.
Their prime concern with resin content is to have enough resin to laminate
the board sufficiently strongly to survive the thermal conditions of the
manufacturing process.
You glanced on glass fiber weave and its impact and various approaches
have been taken - from routing critical traces at around 10 or 11 degrees from
orthogonal - to now using spread glass where the glass is mechanically spread
and uses less twists per inch in the threads to make it less like a coarse cloth
and be more evenly distributed. One challenge here is this construction makes
it harder for the resin to flow across the glass "boundary" and this means more
resin is needed to ensure a successful lamination. Like a lot of engineering
challenges you trade one effect for another. Interestingly I understand that
spread glass was originally designed to give better results when laser drilling
and that a side effect was a more homogenous Er value. Also there are some
glass alternatives that now have a closer Er to that of the resin system. (I am
old enough to remember the aramid reinforced Thermount that DuPont used
to manufacture which had similar benefits...
Kind regards
Martyn Gaudion
polarinstruments.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Richard Allred
Sent: 31 May 2016 13:45
To: Istvan Novak
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Variation of PCB Dielectric Properties
Thanks for the comments, they helped me clarify my thoughts.
As you guessed, I am interested in finding the statistical distribution of the
dielectric "constant" property across high volume manufacturing so I can
understand how the absolute delay of the line varies. Determining the output
statistical variation of a system, given the input variable distribution, is
one of my current pet projects.
I was able to find a very interesting presentation by Gary Brist of Intel (from
the early 2000's) where he discusses in extreme detail the manufacturing
process variation for FR4. Slide # 91, 97 and 106 contained the e_r
information was was after.
https://www.jlab.org/eng/eecad/pdf/053designop.pdf
The bottom line is that e_r varies due to the resin content and the spatial
proximity of the copper trace to the glass bundle (weave effect). My guess is
that if there is an updated study on current materials for high speed PCB that
it is likely proprietary.
Regards,
Richard Allred
On Tue, May 31, 2016 at 6:02 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
wrote:
Vadim,
I agree with what you say. In this particular case though the
question came from someone working for an EDA company, making it much
less likely that they can affor or want to go into the business of
designing/evaluating printed circuit boards themselves. Until we get
to a point that the glass and resin electrical properties differ much
less and they are described in more detail on the data sheet, this
question will remain just partially answered. Though to the credit of
laminate and pcb vendors, they have come a long way to supply more
data. A lot is already posted available for everyone and even more is
available with nondisclosure agreements.
Regards,
Istvan Novak
Oracle
On 5/31/2016 3:46 AM, heyfitch (Redacted sender heyfitch for DMARC) wrote:
Hi Richard -
I may not exactly be answering your question here.....
The more you specify to a fab house the less you leave to chance.
You can pick a specific dielectric from a menu of offerings with a
known thickness and a RC (resin content). The so called "pressed out
thickness"
would depend on the % of copper fill. The default number is usually
given for 50%, but you can ask a fab for the number for your design
before you give'em a go. The trace width is what a fab adjusts to hit the
target Z.
They don't tweak RC for this purpose. Higher RC dielectric usually
has lower Dk and higher Df. Some dielectric vendors show explicitly
in their datasheets the Dk values for each available option of RC.
The effective Df is very strongly affected by the choice of copper foil
(RTF, VLP, HVLP).
That is if you roll the loss due to copper surface roughness into the
dielectric's Df parameter. It's not necessary to do so if you have
built enough many coupons to unambiguously separate Df and copper
surface roughness parameters in you simulation model (by way
of deembeding generalized model s-parameters.)
This is all good but here comes a reality check...
I have seen internal data from a reputable fab of their own impedance
coupon measurement. To my surprise, the impedance values were
distributed almost uniformly between -10% and +10% of the target.
They did not show any outliers, which made me think the fab used this
coupon measurement - one per panel - for sorting.
With such a uniform distribution their yield must have been quite low.
(For microstrips, the actual Z is also affected by the amount of
over-plating and the solder mask, changing it by up to 3-4 Ohms.).
To muddy up this already confusing picture, one should consider how
fabs use Polar Instrument HW and SW - the de-facto standard with them
- to determine impedance of a panel coupon, which leads to a systematic
error.
But that is a whole other can of worms that I will not get into here.
My recommendation, if you asked for one, is to include you own
connectorized coupons in your design, and measure them; then fit
GMS-parameters with the model. And, yes, "waste" space on the panel
for the coupons; this will make you many friends among project
managers left and right. ;). But, in the end, you will know exactly
the impedance, the dielectric, and surface roughness model
parameters. If you stay with the same fab thru many designs - and
avoid fab brokers - you may even collect useful data on how consistent this
fab is.
Best regards,
Vadim Heyfitch
Sent from my phone
On May 29, 2016, at 6:03, Richard Allred <richard.allred@xxxxxxxxx>
wrote:
Greetings,
I am aware that typical PCB manufacturers usually guarantee some
impedance target (+/- 10 or 15%) for high speed traces and that they
may use any number of manufacturing controls to achieve this. The
result is that the only way to know the geometric dimensions of a
given sample is to cross-section it.
What I am interested in is, what kind of variation can be expected in
the effective dielectric properties due to the PCB manufacturers
tweaking of the glass/resin ratio and the geometrical variation? Is
anyone aware of a published study that reports this?
Kind regards,
Richard Allred
www.SiSoft.com
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