[SI-LIST] Re: VIH(AC)& VIH(DC) DDR3
- From: Tesla <emcesd@xxxxxxx>
- To: hermann.ruckerbauer@xxxxxxxxxxxxx
- Date: Tue, 14 Aug 2012 09:13:47 +0800 (CST)
Hi, All
The timing or voltage requirement on DDR3 signal is refered to pin of chip or
die of chip? can not find a indication in JEDEC's standard.
Tesla.
At 2012-08-11 23:09:50,"Hermann Ruckerbauer"
<hermann.ruckerbauer@xxxxxxxxxxxxx> wrote:
>Hello,
>
>your signals need first to cross the AC level to give the Receiver some
>overdrive for fast switching and short input setup times.
>Once your receiver is switched the level is allowed to go below the AC
>level (min) worst case back to DC (min).
>Reason for this definition is the difficult signaling with Point to
>Multipoint connections that cause a lot of reflections.
>
>You can close your timing budget either with the VIH AC175 or the VIH
>AC150. I would need to check in detail, but there should be different
>setup/hold times given if you assume one or the other level (maybe also
>just the derating is different...)
>So if you can not provide the DRAM enough swing to reach Vref + 175mV
>you can also work with Vref + 150mV, but you have to accept worse
>setup/Hold times ..
>
>Hermann
>
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>schrieb Balamanikandan K:
>> Hi,
>> 1. I would like to know the difference and importance of AC & DC Logic
>> input levels (VIH(AC)& VIH(DC) ) for single-ended signals in DDR3.
>>
>>
>> 2. For logic High (input) , should the signal level be higher than VIH
>> (AC)min or VIH(DC)min?
>>
>> 3. What is the importance and meaning of VIH(AC 175) and VIH(AC 150)
>>
>
>
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