[SI-LIST] Re: VHDL problem
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 19 Dec 2011 11:32:49 -0800
VHDL syntax questions are pretty far afield of signal integrity.
arch.comp.vhdl is one of the better places to get VHDL help.
VHDL requires that value resolutions occur in front to back order. You
probably did not define lenInt, and/or lenFra earlier in the compilation.
Steve.
On 12/19/2011 10:34 AM, Wang Chao wrote:
> I wrote a small package in VHDL, but when I compiled this program, I
> got an error that I can not find solution , here is the program(i
> removed the not necessaary)
>
> use STD.TEXTIO.all;
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.NUMERIC_STD.all;
> package ufix_pkg is
> type ufix is array (INTEGER range<>) of STD_LOGIC;
> end package ufix_pkg;
> package body ufix_pkg is
> function ufix2slv(arg : ufix(3 downto 0); CONSTANT lenInt:integer;
> CONSTANT lenFra:integer) return std_logic_vector is
> variable result: std_logic_vector(lenInt+lenFra-1 downto
> 0):=(OTHERS=>'0');
> CONSTANT LenArgInt:integer:=(ufix'left)+1;
> CONSTANT LenArgFra:integer:=0 - ufix'right;
> variable minLenInt, minLenFra:integer;
> begin
> result :=(OTHERS=>'0');
>
> return result;
> end function ufix2slv;
> end package body ufix_pkg;
>
>
> For the line "CONSTANT LenArgInt:integer:=(ufix'left)+1;"
> the compiler shows an error of "ERROR:HDLParsers:3427 - "......Line
> 19. Unconstrained array type is used as prefix for attribute left. "
>
> I do not why. I saw so many times the same structure to read the
> attribute from Unconstrained array in standard lib, but Why I can not
> use it.
>
>
> Thanks
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Steve Weir
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