[SI-LIST] Undershoot or Overshoot Issue at Die Level
- From: "Dean Fitzgerald" <deanrfitzgerald@xxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 20 Jun 2006 08:12:07 -0700
Hello Si-List,
I am using Cadence's SigXplorer and am fairly new at interpreting
the results of IBIS simulations.
I am interfacing a fairly new processor to some mobile DDR memory.
In the layout, the parts are right next to each other. According to
the simulator (when set to fast, not typical or slow). I am violating
the Overshoot/Undershoot voltage level at the DDR die (the pin
name with the lower case "i" at the end of it in the simulator).
At the package pin (without the lower case "i") there is not an issue.
No matter what I do with the transmission line impedance (in
simulation), I can't tame that overshoot. When I add series
resistance, I can then tame it.
This is a wide bus, and I really don't want to add that many extra
parts in my rather space limited design.
The processor vendor says, yes, you need those resistors. But the
processor vendor also says that they are not high speed experts
(which begs the question on how they actually specify their I/O
drivers in their silicon ... THAT is a different topic).
The memory vendor says that the overshoot/undershoot specification
is only in respect to package level, not die level.
My first conversation with a high speed consultant kept flipping back
and forth between (they're so close, you shouldn't need resistors) to
(it's the edge rate that matters and the signal at the die that matters).
So, for those who have lived and breathed SI for some time, I welcome
knowledgeable discussion on this.
-Dean
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