[SI-LIST] Two workshops in DesignCon 2012.

From: "Aveek Sarkar" <aveek.sarkar@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Thu, 19 Jan 2012 23:18:14 -0800
Hi everyone
 

If you are in DesignCon 2012, we would like to invite you to the two
workshops that Apache Design Inc (an ANSYS subsidiary) is hosting. I have
appended the details below.

 

There is no cost to attend the workshops, but registration is required.
Please register for your complimentary Expo Pass and select one or both
workshops during the registration process.

 

Thanks and see you in DesignCon,

Aveek.

 

 

 

 

Session SS-200: CPS Methodology for Cost-Down and/or Reliability

 

Wednesday, February 1, 2012 - 10:15am to 12:15pm

Ballroom H, Santa Clara Convention Center

 

This session discusses how the performance and cost demands of today's chip
designs require a comprehensive chip-package-system approach to analysis.
Industry experts will share their insights and expertise with case studies
and real design examples for chip-package-system (CPS) convergence, and will
discuss various aspects of analysis methodologies and technologies in terms
of modeling, extraction and simulation.

 

Featured Speakers:

Dr. Mondira Pant, Intel

Power Delivery Network Design of Modern Microprocessors: Getting it Right
the First Time

Dr. Amit Agrawal, Cisco

Signal and Power Integrity Challenges for High Speed System Board Design

 

 

Session SS-201: CPS for 3D-IC and Power-Thermal-Mechanical-Electrical
Applications

Wednesday, February 1, 2012 - 2:00pm to 4:00pm

Ballroom H, Santa Clara Convention Center

 

This session focuses on the challenges created by 3D stacked die and 2.5D
Silicon Interposer with TSV chip designs. Industry experts will examine
modeling and simulation needs for 3D-IC design and explore methodologies for
power delivery network analysis, chip-to-chip communication, and thermal
integrity using real case studies.

 

Featured Speakers:

 

Dr. Tim Hollis, Micron

Modeling and Simulation Challenges in 3-D Memories

Ivor Barber, LSI

Modeling and Simulation Challenges in Evolving 3D-IC Formats

Dr. Simon Burke, Xilinx

Challenges and Solutions to Practical 3D-IC Design

 



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[SI-LIST] Two workshops in DesignCon 2012.

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