J. - You could follow this link and see 'generically' how modules are put together from a modeling and termination perspective. ..mike http://www.jedec.org/DOWNLOAD/pub21/HotDDR/config_DDR_Modules.PDF =20 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Jai Dhar Sent: Wednesday, November 23, 2005 8:22 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Two SDRAM ICs Hello everyone, I have been an avid reader of this list for quite some time now, and I would like to start by saying how thankful I am for all the great info provided here! I'm a university student in my final year here in the University of Waterloo (Canada), and have been designing boards with increasing complexity over time... bringing me to my first question! I am designing a board with an FPGA on it and some SDRAM - now, since 32-bit wide SDRAM is apparently becoming harder to get nowadays, I would like to stay away from it due to sourcing issues. Ideally, I would like to get two x16 Micron ICs to form a x32 bus, but I'm not sure due to layout constraints. I only have a 4-layer to play with, so I'm wondering what the best configuration for this would be, and if it's at all possible or not. There will be nothing else on the bus, just the DRAM coming from the FPGA. The stackup is a basic S-P-G-S, and I don't have any controlled impedance to play with. I currently have a similar board, except I placed each DRAM IC on it's own bank of pins, so I didn't have to share any lines. They were close enough to the FPGA such that I didn't need termination (except on the clock) - and this will only be running at 80 MHz max probably, as the FPGA won't let it go any faster. So, with those points in mind, is this something that can be tried? I'm more concerned about how to physically place the ICs - ie, should it be like a multi-drop style where one is farther down the bus than the other.. or should I try to fork the bus and keep everything equal. I would think forking the bus is the best approach, but this seems to be really difficult on a 4-layer with only 2 signal layers to work with. Since DRAM ICs have their Data pins on one side, and those aren't shared, I can easily rotate the ICs such that they are on the outside. But the inside will be a mess since all those pins are shared. Any help is appreciated! Thank you kindly, J -- Open-source hardware at http://www.fps-tech.net -- Open-source hardware at http://www.fps-tech.net ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu