[SI-LIST] Re: Transition time constraint for TSMC 0.18 design
- From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
- To: <gunni@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sun, 6 Nov 2005 20:17:52 -0800
Hello, Unni,
Surely the load is specified for "design constraint of 500ps transition
time"?
A good place for general information on timing test loads would be the
interface specifications for the buffers in the I/O library. Some timing
test specs use a capacitive load. Some use a resistive load. Others, such
as LVDS, use both.
It might be helpful to talk to TSMC application engineers. Do customers
need capacitive-equivalent timing tables, for example for chip-level
synthesis (I/O acting as receiver)? Are capacitive-equivalent timing tables
needed for I/O acting as drivers? What load is used for the "clk-to-Q"
timing for the datasheet?
In the past, I have found it helpful talk to someone in the test lab. They
can be very helpful in explaining what their capabilities are for chip
testing, particularly the types of I/O test loads their test equipment can
handle. Having at least one simulation at that same load can help with
SPICE model validation.
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Unni Gangadharan
Sent: Friday, November 04, 2005 3:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Transition time constraint for TSMC 0.18 design
Hi,
Currently I am working on a 0.18um TSMC design that is meeting timing and a
month and a half away from tape-out. There is a request for adding an
overall design constraint of 500ps transition time.
Presently, the library is characterized for up to 2ns range. The frequency
is 100MHz. With the library default transition number the chip has worst
case 1.5ns transition time. With a .5ns transition time the area blows up
by 15%. Typically what are the design constraints we should set in terms of
capacitance and transition on the signals?
Any information regarding this query would be highly appreciated.
-Thanks
Unni
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