[SI-LIST] Re: Timing equations - help
- From: "hreidmarkailen" <hreidmarkailen@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>, <Cortex.Chen@xxxxxxxxxxxx>, <kranthi.paturi@xxxxxxxxxxxxxxxxxx>
- Date: Fri, 1 Sep 2006 22:09:26 -0400
kranthi,
spla yer krunge ...
That is, draw a schematic, label it with delays, generate a timing diagram
and do the work.
Here's a hint...
1. I assume "common clk" arrangement, where 2 clk buffers are used - one to
drive a copy to the driver and one to the rcvr.
2. If so, you need to refer everything to a single time reference: the "main
clk transition" feeding the clk buffers, or however you wanna define it. It
could even be the xmt or rcv clk at some ref. point in the circuit but
that's more complicating.
Then, clkxmt has a delay to the driver and clkrcv has a delay to the rcvr,
both relative to the clk behind the curtain. And "delay" here means total
path: buffer, board, rcvr pkg+die.
The two clk delays are subtracted to get a skew: a-b = skew could mean it
needs to be added in the budget, with b-a definition meaning it must be
subtracted in the budget ... or vice versa. And if the setup margin adds it
then the hold margin eqn subtracts it, and vice versa.
You're free to choose, but you must communicate your definition if you don't
want to inflict similar pain on posterity. It's like the situation of The
Doomsday Machine. It's no good unless you announce it; if you don't then it
fulfills its mission.
Evidently, your document authors haven't provided the skew definition.
Naughty naughty. It's further complicated if you define clk jitter of each
clk buffer, so the final budget then has a 'differential clk jitter'
component, but that's left as an exercise for the reader.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Cortex.Chen@xxxxxxxxxxxx
Sent: Thursday, August 31, 2006 1:34 AM
To: kranthi.paturi@xxxxxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Timing equations - help
Kranthi,
For mathematics, you're right, however, actual equation indicates min =
margin for pessimistic or worst case and thereby your confusion occurs.
Regards,
Cortex
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of kranthi
Sent: Thursday, August 31, 2006 12:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Timing equations - help
Hi,
I have a doubt in timing equations for calculating the setup and hold
margins.i referred few documents but, were very confusing and so I did
not have another option other than posting it on this group.
The cause of confusion is the clock skew parameter.some documents
subtract it for calculating the set up margin and add it for calculating
the hold margin while others do the opposite way.One point to be noted
is that the skew can be positive or negative.So, what is the exact way
in which the skew should be accounted.i have a general conception that,
If the clock skew is positive then Tclk_skew should be added in
setup_margin equation and subtracted in hold_margin equation, and when
the clock skew is negative it should be taken the opposite way.Is this
conception correct?
Please help me on the exact way of considering this parameter(clock
skew) in estimating the setup and hold margins.
Best regards,
Kranthi
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