[SI-LIST] Re: Timing analaysis for Interfaces
- From: msmurthy murthy <madiras@xxxxxxxxx>
- To: "List (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Sat, 18 Oct 2003 22:23:15 -0700 (PDT)
Hi all,
I performed signal integrity simualtions for PCI, GMII/RGMII, DDR & QDR
interfaces. I simulated these interfaces on non-lossy transmission lines. I am
doing timing analysis for these interfaces. I would like to know what
parameters I should consider for timing analysis and the method the others
following in tying their SI simulation results to timing analysis.
What I am following is that I take valid times I measured at Vih levels (at
receivers) along with the clock periods I got from the SI simulations and
perform timing analysis with reference to ideal valid times and ideal clock
periods. Then I will be considering parameters like pcb delays, cross talk
information on the simulated timings thus attempting to arrive at worst case
margins for set up hold times at the receivers.
Thanks,
Murthy
Massimo.Panonzini@xxxxxxxxxx wrote:
David,
SerDes is typically referred to PMA layer of IEEE8023.3 that is re-sync and
serial/parallel (TBI) conversion,
after that on parallel side there is PCS layer in which 10B/8B decoding is
performed and Autonegotiation (if needed) obtaining the decoded GMII
interface (8 data bit + 2 controls).
usually PHY device include PCS giving out GMII interface while serdes only
PMA giving out TBI.
So if your serdes includes 8b/10B you are only missing Autonegotiation.
regards
Massimo
-----------------------------------------
Massimo Panonzini
OMSN R&D Alcatel Italy
via Trento 30 20059 Vimercate (Milan)
massimo.panonzini@xxxxxxxxxx
tel: +39-039-6863279 fax: +39-039-6863590
------------------------------------------------------------------------------------------------
"...and if you listen very hard, the tune will come to you at last
when all are one and one is all, to be a rock and not to roll..."
David Shapiro
t.com> cc:
Sent by: Subject: [SI-LIST] SerDes vs. PHY for Gigabit Ethernet
si-list-bounce@fr
eelists.org
17/10/2003 14.56
Please respond to
DavidS
Hello,
I want to drive GigabitEthernet on fiber optics.
Parallel data format is RGMII.
Does anyone know, if I can use simple SerDes supporting RTBI format (having
8 to 10 bit encoding), instead of a Gigabit Ethernet PHY device ?
Are RTBI and RGMII compatable ?
If I use Serdes what functionality I would not be able to support ?
Thanks.
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