[SI-LIST] Re: Time step resoution in Hspice

  • From: "Craig Clewell" <cclewell@xxxxxxxxx>
  • To: <sogo.hsu@xxxxxxxxxxx>
  • Date: Tue, 12 Oct 2004 07:24:27 -0800

Sogo, 

I think the option you are looking for is RELTOL.  This sets the
relative accuracy of the calculated voltages and currents.  It is a
ratio of the error allowed to the signal level.  For instance, if you
were to set RELTOL to 0.01 the resulting voltages and currents
"calculated" would be within 1% of their "real" values.  You can also
investigate setting the VNTOL and ABSTOL.  These 2 control the accuracy
of the voltage and currents respectively.

Also, note that when using a PWL source spice will force a time-step at
every corner in the driving waveform.

You also may want to set the 4th parameter in your .TRAN statement.
This parameter sets the maximum step size.

Spice will use the minimum of all the limits you set to limit the size
of the time step.

Another thing, you may have to sharp of a corner on your source which
causes artificial ringing not found in reality.  You can add a gate
between your source and the rest of your circuit to circumvent this
problem (round the corner).

Craig

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sogo Hsu
Sent: Monday, October 11, 2004 7:40 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Time step resoution in Hspice


Hi Gurus,

As digital signal speed does keep getting faster, the difficulty of 
meeting jitter requirement is more rigorous. Recently, we tried to 
characterize jitter mechanism for SERDES. First of all, we conducted 
a simple scenario for observation of signals transmitting through T-
line element. The sp file is shown as below.

=======================================================
.option accurate
.option converge=1 gmindc=1.0000e-15

Vgp5 nd_in11 0 PWL 0N 0.5V, 0.39N 0.5V, 0.4N -0.5V, 0.79N -0.5V, 
0.8N 0.5V, R 0N

Rin1 nd_in11 nd_in11t 50

Tbreakout nd_in11t 0 out_p 0 Z0=50 Td=1ns

Rt1 out_p 0 50

*Analysis
.tran 100ps 1us start=0ns
.option post probe
.probe PAR('v(out_p)')
.probe PAR('v(nd_in11)')
.END

=====================================================
The voltage source is a clock signal switching between -0.5V to 0.5V 
with 1.25GHz frequency. Theorectically, results of Vout should be 
the same as the source signal. But, it seems that the cycle width of 
signals at Vout is not always to be 800ps. At time point near 200ns, 
its value is 800.0001ps. While at 600ns, its value is 800.0143ps. 
And at 800ns, the value is 799.9574ps. 

We don't realize why this difference occurs. Does there any method 
to increase the precision of simulation result to eliminate this 
difference? Or something wrong in the spice circuit linkage? The 
little turbulence in time will affact the characterization of 
jitter. Besides, there seems to be a overshoot about 8mV at the 
rising edge of signals at Vout. 

Thanks in advance!

Sogo Hsu, Ph. D.

Simulation center/Foxconn




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