[SI-LIST] Re: Time step resoution in Hspice
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: <sogo.hsu@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 12 Oct 2004 10:37:28 -0400
Just out of curiosity, do the results differ if you remove the transmission
line? This would remove one variable from the picture.
SPICE's internal timepoints are not uniform, and generally do not line up
with zero-crossings and points where you want information. This forces
SPICE (or the downstream analysis program) to interpolate between adjacent
timepoints, and sometimes the result isn't exact because the waveform has
some curvature which is probably ignored.
You can reduce that by forcing smaller internal timesteps, giving more
"density" to the raw data.
In your case, you requested a timestep of 100ps. Having "errors" of 45fs
out of 100ps is better than a part per million.
HSPICE has a tendency to allow its internal timestep to get quite large
(compared to the requested timestep, 100ps in your case), which forces it to
rely on those interpolations even more. With nothing nonlinear in your
circuit, HSPICE's algorithms might be taking this to extremes. There are
one or two .OPTIONs that control this. I forget which one(s), but you can
basically tell HSPICE not to make its internal timestep larger than the
requested timestep. It does make your simulations run slower, and your
output files bigger. That's the price you pay.
At some point, the inherent numeric resolution of SPICE's engine might start
to get in the way. For example, if you were to represent t = 800ns as a
straight 32-bit mantissa (which is not how computers handle floating-point
numbers, but I'm using it to illustrate), one bit of resolution would be on
the order of 0.2fs, which means there is a potential error of at least that
much at every step along the way. Using 64-bit variables and math would be
better. Even if SPICE's internal representations were perfect, passing the
data from the engine to the downstream processing tools might include
truncation, maybe to 32-bit floating-point numbers which have less than a
32-bit mantissa.
If I'm not mistaken, HSPICE sometimes adds tiny capacitances as well as the
gmindc conductances at each node, which among other things gives you a tiny
mismatch at both ends of your transmission line and might be causing some of
the apparent jitter and the overshoot you see (just a wild guess). You have
some control over this through the .OPTIONs.
Transient simulations in SPICE works differently when there are nonlinear
devices anywhere in your network being simulated. There were none in your
test case. With nothing nonlinear, SPICE doesn't need to do repeated Newton
iterations; it can calculate every value "precisely" at every timepoint
without needing to guess, then estimate the errors, then iterate again until
the error is sufficiently small. I believe this means that all of the
various TOLerances (ABSTOL, VNTOL, RELTOL, etc., which also go by different
names in HSPICE) would have no effect. But with anything nonlinear in the
circuit, SPICE must do repeated Newton iterations, and the flow is quite
different, including "backing up" at rejected timepoints, etc. That's about
all I know about it, but just be aware that this difference happens. Thus,
your testcase might even be too simple.
After having said all this, I wonder if more attention should be paid to the
overshoot, which in theory shouldn't be there. Maybe finding and fixing the
cause of that, would eliminate your apparent jitter too. At some point this
might become a question for an HSPICE FAE to tackle.
Regards,
Andy
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