Jeff,
If your design is limited to simple through hole vias, then two hole sizes
are required - finished hole size to make sure components can be inserted
and drill hole size to insure required signal integrity performance.
But there is more!
Dual Diameter drilling is being evaluated to insure sufficiently large holes
to allow component insertion, and smaller hole size on the other layers to
improve impedance characteristics to insure required signal integrity
performance. This adds a finished and drill diameter for the send hole size
and a transition depth.
Back drilling is now being done on both sides of a board. So one needs to be
able to define the drill diameter and depth of back drilling the Top and
Bottom side of the board.
IPC-2581 already supports finished and drill hole and the back drilling on
top and bottom of a board. It would be straightforward for them to enhance
IPC-2581 to support in a standard way Dual Diameter drilling.
Walter
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Jeff Loyer
Sent: Wednesday, January 6, 2016 10:24 AM
To: Gert.Havermann@xxxxxxxxxxx; SI <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: AW: AW: Re: AW: AW: Re: How to specify via hole sizes
Thanks for all the great replies. Based on this and other research, my
current thinking is that:
1) Yes, we should specify O.D. and I.D., but I’m told manufacturing
folks probably won’t understand it well in those terms. Instead we might
use the term “drill size†to represent O.D. and “finished hole sizeâ€
for I.D., each with its corresponding tolerance.
a. I’m not sure how well the various tools support this, I believe
most assume a single size for vias. Like Alexander, I’ve had to build
unambiguous drill charts manually in order to know exactly what I was
getting.
2) I don’t think the exchange formats support multiple drill sizes.
In ODB++, for instance, I think there’s only a single value for hole size;
I believe that’s assumed to be “drill sizeâ€.
a. Resolving this might help our 3-D simulations.
3) I believe the industry needs to gain consensus on exactly how we
should specify these two dimensions in an unambiguous manner. I’m still
not sure who in IPC I might approach about this.
Interesting comment about anti-pads. Like Gert, I’ve had documentation
indicating that’s not allowed to be modified without informing me, but
it’s probably a good thing to reiterate in a fab drawing when vias are
carefully constructed.
Jeff Loyer
Signal and Power Integrity Product Manager, Altium
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Havermann, Gert
Sent: Wednesday, January 6, 2016 1:51 AM
To: SI
Subject: [SI-LIST] AW: AW: Re: AW: AW: Re: How to specify via hole sizes
Hi Alex,
1) I have made bad experience with defining OD and ID in the same Drill
Document. When I separate the Drill files, each drill will be in either one
or the other drill file, not in both. This process is also used for blind
and buried vias. The EDA software creates a thru drill file (with oly thru
vias being present), and a bolind via drill file (with only the blind vias
of the selected Layer being present)...
But I believe that PCB-Houses also have different preferences and maybe they
would prefer ddifferent data, but since I define separate files, there have
been no errors.
2) When I define OD for a via, then I design the Pad accordingly. I would
never allow the PCB House to change Pad sizes, tracewidth or Stack-up
without prior notice and my written conformation. That’s one of the
important notes in my specification.
But you are correct that by just defining the drills to be OD without taking
care of the Pads can result in Problems.
BR
Gert
----------------------------------------
Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender des
Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende
Gesellschafter:
Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W. Harting, Maresa
Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG, HARTING Beteiligungs
GmbH & Co. KG; Generalbevollmächtigte Gesellschafterin: Dipl.-Hdl. Margrit
Harting
-----Ursprüngliche Nachricht-----
Von: Alexander Ippich [mailto:alexander.ippich@xxxxxxxxxxxxxxx
<alexander.ippich@xxxxxxxxxxxxxxx>]
Gesendet: Mittwoch, 6. Januar 2016 10:29
An: Havermann, Gert; SI
Cc: Alexander Ippich
Betreff: AW: [SI-LIST] AW: Re: AW: AW: Re: How to specify via hole sizes
Gert,
Agree with most of your statements. But wanted to state two additions /
modifications:
1) generating two drill files, one for outer diamteter (drilled hole size)
and one for inner diameter (finished hole size).
I would discourage this. As both files should show the same x/y-coordinates,
why have them twice? Typically the hole sizes are listed in a table on the
fab drawing. My recommendation would be to use only one drill file and have
both, ID and OD in the drill table on the fab drawing where needed. For
those tools, where it is not necessary, just state ID.
The same table would also show the diameter tolerances, making it very easy
for the PCB shop to understand your requirements.
2) definining OD to control capacitive load Please be aware, that (if not
explicitly forbidden) many PCB shops will adapt the antipad sizes to
optimize their process. The larger the antipads, the less risk for a PWR/GND
to via short. On the other hand, the smaller the antipads, the larger the
copper web inbetween the vias of an array component. Also, most PCB shops
control the feature sizes for signal layers but for PWR/GND layers, very
often it is only checked, that there are no copper residues / shorts. So
clerances tend to be larger than nominal.
So if you define the drill bit but don't take care about the antipad sizes
(in the finished board), this will not help.
Best regards,
alex
----------------------------------------------------------------------------------------------------------------------------------------
Alexander Ippich
Senior Signal Integrity Engineer
OEM Marketing Europe
Tel.: +49 170 / 63 68 571
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>] Im Auftrag von Havermann, Gert
Gesendet: January 06, 2016 09:47 AM
An: 'SI'
Betreff: [SI-LIST] AW: Re: AW: AW: Re: How to specify via hole sizes
Happy new year everyone.
Back to the initial question I would like to add that there are very good
reasons to define the inner diameter, and that’s why this has become
widely accepted practice (unfortunately it isn't standardized, thus you have
to make shure to specify it in the fab notes). Press-Fit connections (aka
compliant pin, aka eye of a needle pin) need a tight tolerance inner
diameter of the via.
For impedance controlled vias I prefer to define the drillbit diameter as
this is important for the capacitive load of the via. When I have both in
the same design, then I create two separate drillfiles and drilltables and
define one to be ID and the other to be OD (same Documentation process as
for HDI). Every EDA tool can do this.
BR
Gert
----------------------------------------
Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender des
Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende
Gesellschafter:
Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W. Harting, Maresa
Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG, HARTING Beteiligungs
GmbH & Co. KG; Generalbevollmächtigte Gesellschafterin: Dipl.-Hdl. Margrit
Harting
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>] Im Auftrag von Lee Ritchey
Gesendet: Dienstag, 5. Januar 2016 18:11
An: alexander.ippich@xxxxxxxxxxxxxxx; 'Istvan Nagy'; saardrimer@xxxxxxxxx
Cc: 'SI'; 'Jeff Loyer'
Betreff: [SI-LIST] Re: AW: AW: Re: How to specify via hole sizes
My fabricators always add thieving to even out the plating in holes that are
close together and far apart. I don't have problems with large variations
in plating thickness.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>] On Behalf Of Alexander Ippich
Sent: Monday, January 4, 2016 11:17 PM
To: Istvan Nagy <buenoshun@xxxxxxxxx>; Lee Ritchey
<leeritchey@xxxxxxxxxxxxx>; saardrimer@xxxxxxxxx
Cc: SI <si-list@xxxxxxxxxxxxx>; Jeff Loyer <jeff.loyer@xxxxxxxxxx>;
Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] AW: AW: Re: How to specify via hole sizes
Hi Istvan,
Without knowing more about the particular process that European PCB shop was
using, it is very hard to tell, what exactly they did. They may have used a
double pass plating process, where the small vias got plated twice and the
larger vias plated only once (by drilling them between the 1st and 2nd
plating step). But I would not understand why anyone would do this.
All PCB shops are driven by cost, cost, cost. So they try to use the most
cost effective process. Any additional process steps, longer plating
exposure times,... cost more money, so everybody tries to avoid them.
As explained in my original statement, it is most difficult to get the
copper in the small vias. The larger vias are easier (unless we talk about a
single, isolated small hole compared to a large number of bigger holes that
are very close together). So PCB shops will try to get enough copper in the
small holes (to satisfy OEM specs regarding Cu plating). This typically
automatically guarantees that enough copper is in the larger holes.
One limitation are larger press fit holes with very tight tolerances. With
this approach, the plating in the larger holes may already exceed what is
acceptable for FHS minimum sizes. Because of this, it may be necessary to
use a special plating process that limits the plating into the larger
pressfit holes but still get enough copper in the small via holes.
But then again, after 20 years on the PCB manufacturing side, I can
definitively say, we always had less copper in small vias compared to large
PTHs.
Best regards,
alex
----------------------------------------------------------------------------------------------------------------------------------------
Alexander Ippich
Senior Signal Integrity Engineer
OEM Marketing Europe
Tel.: +49 170 / 63 68 571
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Ursprüngliche Nachricht-----
Von: Istvan Nagy [mailto:buenoshun@xxxxxxxxx ;<buenoshun@xxxxxxxxx>]
Gesendet: January 05, 2016 04:58 AM
An: Lee Ritchey; alexander.ippich@xxxxxxxxxxxxxxx; saardrimer@xxxxxxxxx
Cc: 'SI'; 'Jeff Loyer'
Betreff: Re: [SI-LIST] AW: Re: How to specify via hole sizes
Hi,
Several years ago I was working in Europe and with local PCB fabs. One of
them told me that data with the thinner hole more copper. I didn't
misunderstand it.
Today I asked my current Taiwanese fab and they said:
10mil-drill vias: copper thickness is 1.0mil, larger PTH holes: copper
thickness is 1.1mil.
Either the data was inaccurate (I doubt it) or their process is different.
Regards,
Istvan Nagy
-----Original Message-----
From: Lee Ritchey
Sent: Monday, January 04, 2016 9:00 AM
To: alexander.ippich@xxxxxxxxxxxxxxx ; buenoshun@xxxxxxxxx ;
saardrimer@xxxxxxxxx
Cc: 'SI' ; 'Jeff Loyer'
Subject: RE: [SI-LIST] AW: Re: How to specify via hole sizes
Well said!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>] On Behalf Of Alexander Ippich
Sent: Sunday, January 3, 2016 11:47 PM
To: buenoshun@xxxxxxxxx; saardrimer@xxxxxxxxx; Lee Ritchey <
leeritchey@xxxxxxxxxxxxx>
Cc: SI <si-list@xxxxxxxxxxxxx>; Jeff Loyer <jeff.loyer@xxxxxxxxxx>;
Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] AW: Re: How to specify via hole sizes
Istvan,
This looks like some wrong information. Smaller vias are always getting less
copper plating than larger vias (in the same plating step). Think about the
electrical fields in a narrow tunnel that has metalized side walls. You will
get a much lower current density in the small vias, and as a result less
plating deposition. In addition, the exchange of the plating fluid is worse
in small vias.
Bottom line, if small and large vias are plated in the same step, PCB
manufacturers will adapt their plating process to get the minimum copper
requirement fulfilled for the small vias and you will see thicker copper in
the larger vias.
And as Lee already pointed out, there are some fabricators that have better
uniformity and some with worse uniformity. Design is already playing a role
(dense areas get less copper than isolated features) and there are ways to
optimize like thieving patterns.
But in general, if somebody is claiming more copper in small vias and less
copper in large vias, something is very very strange (unless you talk about
copper filling of vias).
Best regards,
alex
----------------------------------------------------------------------------------------------------------------------------------------
Alexander Ippich
Senior Signal Integrity Engineer
OEM Marketing Europe
Tel.: +49 170 / 63 68 571
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx>] Im Auftrag von Istvan Nagy
Gesendet: December 30, 2015 10:46 PM
An: saardrimer@xxxxxxxxx; Lee Ritchey
Cc: SI; Jeff Loyer
Betreff: [SI-LIST] Re: How to specify via hole sizes
Different hole sizes get different amount of copper. One fab told me that
with their process the smallest via holes get 2mils on the walls, while the
larger holes get only 1mil.
Regards, Istvan Nagy, mobile
*** Sent from my BLU smartphone device *** On Dec 30, 2015 9:04 AM, Lee
Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
I always specify drill size. If there is a hole that requires a
finished hole size, I add 4 mils to get the drill size. This allows a
minimum of 1 mil copper in the hole wall which is what most of require.
Works great!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<si-list-bounce@xxxxxxxxxxxxx>]Behalf Of saar drimer
On
Sent: Tuesday, December 29, 2015 12:55 PM
To: buenoshun@xxxxxxxxx
Cc: SI <si-list@xxxxxxxxxxxxx>; Jeff Loyer <jeff.loyer@xxxxxxxxxx>
Subject: [SI-LIST] Re: How to specify via hole sizes
This is a great example where tools actively limit design creativity.
What possibly led to a situation where only specifying one dimension
is satisfactory? This isn't a manufacturing limitation.
It's worse when you want to do something more creative, like having
vias that have different ODs for each layer. I've done this for visual
reasons (using PCBmodE where vias are components), and I'm not sure
there's a legitimate functional reason to do that (is there?)
Cheers,
Saar.
On Tuesday, December 29, 2015, Istvan Nagy <buenoshun@xxxxxxxxx> wrote:
Jeff,
most fabs will manufacture to your ID or OD if you tell them which
one you want. The design tools like allegro and altium works best
wit OD, and you can only specify one or the other. Tools drill file
formats and drill tables only support one diameter per hole. For
designing better use OD as it helps the drc to make sure no pads
drilled away and no drill to xx clearances were violated. The wall
thickness depends on the fab and the hole size, an even the same fab
will give you different numbers each time.
i think the safest is to specify OD and use worst case thin for PI
while worst case thick wall for PTH component pins.
Regards, Istvan, mobile
*** Sent from my BLU smartphone device *** On Dec 29, 2015 11:15 AM,
Jeff Loyer <jeff.loyer@xxxxxxxxxx <javascript:;>>
wrote:
One thing that has bothered me forever is the ambiguity in
specifying via hole sizes. To my mind, there are instances where
I might want to carefully specify either, or both of, the outer
and inner diameters
(O.D.,
I.D., respectively) of the via “columnâ€Â. But, that
seems
difficult (if
not
impossible) to do with current common drill specifications (what a
“finished hole size†is seems to depend on context,
some folks
enter the approximate drill size here). Can folks tell me how
they ensure they get the correct diameters for the following cases:
1) Signal integrity: I care about the O.D. This is going to
be
(approximately) the size of actual drill used.
2) Mounting holes: I care about the O.D. This is going to be
(approximately) the size of actual drill used.
3) Press Fit connectors: I care about the I.D. This is the
actual drill size minus plating thickness.
4) Power Integrity: I care about both, I want to know the
total
copper
connecting my layers.
What does your drill chart look like that ensures you get what you
need?
I’ve used “drill size†with some tolerance plus
a
“finished hole sizeâ€Â
with
its tolerance, but that seems ambiguous. At this point, I think
we need
to
specify a “hole diameter†with a corresponding
tolerance, and
a plating thickness range. While I would prefer to specify both O.D.
and I.D.,
each
with its corresponding tolerance, I’m told that folks in
the
industry
won’t
know what I’m talking about if we do it that way. What has
worked best
for
folks?
Also, if someone has a key contact within IPC that I should be
talking
to,
I welcome that information too (please send it to me only to limit
unwanted
distribution of anyone’s e-mail).
Thanks,
*Jeff Loyer*
Signal and Power Integrity Product Manager, Altium
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