[SI-LIST] Re: The question for HDMI compliance spec & Debuging method
- From: "Brian Baek (sebaek)" <sebaek@xxxxxxxxx>
- To: 김창희 <ch80.kim@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 16 Dec 2011 13:48:26 -0800
There are commends below
Regards,
Brian(Seungyong)
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Dear everyone,
This is my first trial to ask question on SI-LIST. Wish everyone is
welcomimgwith my question.
1) when I see the HDMI compliance test report(H/W), the Rise/Fall time spec
is >u.000ps .
why the spec is >ups, not <= (max time limit) ?
I think the rise/fall time should be shorter for better SI performance.
Is there any specific reason for restricting rise/fall time to be larger
than75ps?
It depends, normally HDMI (TMDS signal) is passing thru cable. So, EMI is
another challenge at connector and cable.
If rise/fall time is fast, more energy of harmonics will deliver because the
harmonics fall off with frequency at a 20dB per decade rate up to a frequency
of 1/(pi*rise_time).
2) Now my system has a problem with EYE test on 1080 60p with 148.5Mhz.
The envelope of Rising signal is touching the EYE MASK since the envelope is
too slow. (rise time is 290ps)
Would you please share some methods to make shorter rise time on the
system?
( I tried the pre-Amphasis option for boosting signal, but it causes
criticalovershooting which i can't accept)
* the trace lane impedance is about 100ohm in this system.
I don¡¯t know your measurement point. I believe the most of rise time
degradation happens at ESD Cap and ESD Pad design except connector and cable.
You need to measure TDR waveform and check the biggest drop location for
finding the capacitive structure.
Best Regards,
Chang
[IMG][IMG]
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