[SI-LIST] Re: The margin of IBIS-AMI Serdes simulation

  • From: Ambrish Varma <ambrishv@xxxxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 2 Mar 2016 15:17:14 +0000

Hi Tesla,
Both your questions can be answered with 'It depends'. It may be a good system 
depending on what your requirements are. Are you analyzing a USB3 gen2 (for 
ex), or a PCIe3/4. You will need to analyze the eye height/width at a 
particular BER (requirements for PCIe4 is that the Rx must meet BER 10^-12 over 
the entire jitter range - AKA Jitter Tolerance). What about IL/RL and any 
deviations. 
So you will need to analyze this system in a complete compliance settings with 
other requirements that the specification you are trying to work with.
Best Regards,

Ambrish Varma
Cadence Design System.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Tesla
Sent: Wednesday, March 02, 2016 4:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] The margin of IBIS-AMI Serdes simulation

Hi Experts

i am doing a medium loss 10Gbps channel IBIS-AMI simulation. The channel loss 
is 15dB at 5GHz. After 10Mega bit by bit AMI simulation, an eye diagram with 
0.65UI width and 0.12V(p2p) height is got at the RX die side. Is this a good 
system?How much margin should   i allocate for  AMI simulation?

Good day.

Tesla.
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