[SI-LIST] The PLL simulations
- From: "chen, jinhua" <chen_jinhua@xxxxxxx>
- To: SI LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 27 Aug 2001 13:14:27 -0400
Hi, SIer's
I had a problem with PLL circuit recently. The PLL circuit was
part of Gigabit SerDes device. When the device was tested in the low
temperature, the SerDes got a lots of bit-errors. We figured
out that the low frequency power noise got into the circuit and
the PLL could not lock the clock. Then it caused the high bit-error
rates.
I want to simulate this problem with different temperature, different
supply voltage levels and different noise levels with different=20
frequencies. Theoretically, the HSPICE should be able to do it.=20
I never simulated the PLL before. Anybody can shed some light on
this issue? If the SPICE is not a good tool to do it, any other
tools available to make such simulations?
Thanks!
Jinhua Chen
Consulting Design Engineer
171 South St.
Hopkinton, MA 01748
508-435-1000, ext. 15285
Pager: 8779700234
chen_jinhua@xxxxxxx
EMC=B2 =20
The Enterprise Storage Company
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
