[SI-LIST] Re: Termination of unused PCIe pairs

  • From: "Yun Bai" <Yun_Bai@xxxxxxxxx>
  • To: "otter30" <otter30@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 8 Sep 2010 09:00:19 +0800

Hi Jim,

I think you can just leave GPU's unused PCIe lanes NC. Clarify the PCIe
link width that GPU supports. If it does support downgrade to PCIe x1
lane or x2 lanes, CPU and GPU will negotiation before the link set up.

Above suggestion based on SAS/SATA controller and GbE controller design,
I think you can find the details via GPU maker.

How to terminated the unused lanes, RX pairs should be routed out from
BGA to simplify Debug, no need to termination (or a capacity pad be
placed as test points). For TX pairs, the terminator res can be the test
point, too.

Just FYI.

Best regards,
Yun 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of otter30
Sent: Wednesday, September 08, 2010 5:20 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Termination of unused PCIe pairs

Hello Friends,

I am designing a carrier pcb that provides interconnect between a CPU
module and 
a video processing card.
The video card supports 4x PCIe, but the CPU module has only 2 PCIe
lanes 
available.

Since PCIe pairs are specified to have 100ohm differential impedance, 50
ohm 
resistors to ground ought to 

work on the unused TX pairs. Do I also need a .1u cap in series with the

resistors for the RX pairs?

Thanks,
Jim


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