[SI-LIST] Re: Temperature effect and die backside connection
- From: "O. Laney" <olaney@xxxxxxxxx>
- To: jean-pierre.bouthemy@xxxxxxxxxxxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 22 Nov 2012 15:46:42 +0000
Are you using a back-match resistor? What value?
------ Original Message ------
From: "BOUTHEMY Jean-Pierre" <jean-pierre.bouthemy@xxxxxxxxxxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: 11/22/2012 5:00:57 AM
Subject: [SI-LIST] Temperature effect and die backside connection
>Hello SI Experts,
>I am faced to signal integrity issue when temperature rises above 70°C.
>My clock signal output from 54HCT04 bare die is distorted: it presents non
>monotonic edges that falls down to 1V, ie under next device low threshold (Vil
>= 1.5V). Thus my clock at 3MHz is seen as a 6MHz clock, and my test is FAIL.
>
>When the temperature falls down to ambiant, the signal quality comes back
>perfect.
>
>- Have some of you ever seen such a temperature phenomenon ?
>- Do you have an idea of what happens to the 54HCT04 die ?
>- The backside of the die is left floating: do you think that we should
>connect the backside to VCC potential?
>
>Thank you for your help.
>Regards.
>
>Jean-Pierre Bouthemy
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