[SI-LIST] Re: TRST signal of JTAG I/F
- From: Dimiter Popoff <dimiter.popoff@xxxxxxxxxxx>
- To: <pci-sig@xxxxxxxx>
- Date: Fri, 11 Apr 2003 14:33:23 +0300
Nico,
> Can you tell me what will happen if I do a passive pull-down of that TRST
> input, can I still use that TAP interface of that ethernet controller when
> TRST is continue pull-down? I don't have the on IEEE 1149.1 spec, so I
> can't find an answer on that
Most likely not, the TAP controller may well stay reset all the time,
as you probably suspect. Also, I have my doubts about connecting the
TRST to the system reset, what if there are out-of-reset timing issues
because of that (pretty unlikely, but not unthinkable to me). I'd
hold the TRST a bit longer low than the system reset - but, well, this
may be unnecessary, I am not sure. Of course, connecting them so will
prevent you from JTAGging the system reset line itself or while it
is asserted.
Dimiter
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Dimiter Popoff
Transgalactic Instruments
http://transgalactic.freeyellow.com
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