[SI-LIST] Re: TDR impedance measurement and rise time
- From: Bill Grenoble <billg@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 26 Apr 2009 21:07:14 -0400 (EDT)
Hi,
I got it and I will look at it tomorrow. How do you say "Manana" in
Hungarian? ;) And FWIW, I downloaded with ancient 'lynx', an early, text
only, web browser. I suspect FireFox can also download it.
Best Regards
Bill Grenoble (Old Fart) ;)
On Sun, 26 Apr 2009, Istvan Nagy wrote:
> Date: Sun, 26 Apr 2009 20:17:16 +0100
> From: Istvan Nagy <buenos@xxxxxxxxxxx>
> To: Istvan Novak <istvan.novak@xxxxxxx>
> Cc: Mick zhou <mick.zhou@xxxxxxxxx>, Yuriy Shlepnev <shlepnev@xxxxxxxxxxxxx>,
> si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: TDR impedance measurement and rise time
>
> Hi,
>
> Thanks for these lots of thoughts.
> Actually I also wrote a document about impedance control. I just finished
> today.
> Originally for my colleagues, because we are purchasing some software and it
> would be good if everyone at the (small) company has a clear picture about
> the subject.
> It can be downloaded here (with Internet Explorer only):
> http://www.buenos.extra.hu/iromanyok/Accurate_Impedance_Control.pdf
> If someone can find something wrong or missing in that, then please tell me.
> I know there are lots of aspects about impedance control, but I was asking
> about a specific one, how to measure it in a frequency dependent way.
> Unfortunatelly i can see already that its a problem.
>
> I think the TDR measurements use a wide-band signal (gaussian pulse?) to
> measure, and the result impedance is some kind of average of the responses
> on all the test signals frequency components. If we change the TDR's rise
> time, then its (wide) band shifts in frequency. But I am not an expert about
> TDRs, so maybe its a completely stupid idea.
> Would it be better to measure impedances on test coupons with a VNA? (if it
> is possible) Just because of the single frequency measurement.
>
> regards,
> Istvan Nagy
> CCT, UK
>
>
>
> ----- Original Message -----
> From: "Istvan Novak" <istvan.novak@xxxxxxx>
> To: "Istvan Nagy" <buenos@xxxxxxxxxxx>
> Cc: "Mick zhou" <mick.zhou@xxxxxxxxx>; "Yuriy Shlepnev"
> <shlepnev@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Sent: Friday, April 24, 2009 3:38 AM
> Subject: [SI-LIST] Re: TDR impedance measurement and rise time
>
>
>> Hi Istvan,
>>
>> To get a good correlation, one proven approach is to find a suitable
>> model, which captures
>> all major contributors and signatures that matter, and match the model
>> to the measured data,
>> whether it is TDR or VNA data. If the model is valid for the device you
>> measure, you should
>> be able to get correlation close to the accuracy of your measurement.
>> For instance, if your
>> trace and dielectric geometry is uniform enough that a cross-section
>> geometry and material
>> properties are all what you need to describe the interconnect, you can
>> take the appropriate
>> per-unit-length frequency-dependent resistance, inductance, capacitance
>> and conductance,
>> and simulate what for instance a TDR instrument would show you. You can
>> either blindly
>> optimize the parameters going into the model, or even better, you can
>> assist the optimization
>> with measured parameters on things that you can measure, such as cross
>> section geometry,
>> Dk and trace resistance, inductance (at whatever frequency you can
>> measure them).
>>
>> Even though you can point out certain inter-relations between the f
>> frequency of Zo(f)
>> and the TDR profile, we need to keep in mind that going back and forth
>> between time
>> and frequency domains involves wide-band (theoretically infinite)
>> integrals, so we should
>> not try to correlate a single frequency point to a single time point.
>>
>> The built-in scenarios in the Lossy_trace_parameters_v-w01.xls
>> spreadsheet (posted on
>> http://www.electrical-integrity.com/, Tool download) will show the
>> variations in Zo(f)
>> as a function of frequency and interconnect parameters. You will notice
>> that the conductive
>> loss will create a tendency of negative slope (impedance drops as
>> frequency goes up),
>> whereas dielectric loss creates a positive slope. All-in-all, you get a
>> bathtub curve, where
>> the low and high-frequency slopes and shapes depend on the conductive
>> and dielectric
>> losses independent of each other (reason: at very low frequencies
>> dielectric losses can be
>> neglected; at very high frequencies the conductive loss diminishes in
>> relation to dielectric
>> losses). You can notice that assuming a typical trace skin loss and the
>> worst-case 3.5%
>> Df for an FR4 laminate, the characteristic impedance (magnitude) has a
>> 48 Ohm
>> minimum at 25 MHz, and its value rises to 48.4 Ohm at 100 MHz, 50.36 Ohm
>> at 1GHz
>> and 53.3 Ohm at 10 GHz. This is actually 10% variation over two decades
>> of frequency.
>> Note, however: if you plug in a Df value of 1%, the Zo(f) curve
>> 'flattens out' at high
>> frequencies and you get 50.4 Ohm at 100 MHz and 51 Ohm at 10 GHz, just a
>> little
>> over of one percent variation. This gives us the first clue that a
>> lower loss tangent not
>> only will reduce the signal attenuation, but also the Zo(f) variation of
>> the interconnect.
>>
>> At lower frequencies the impedance variation is much more pronounced,
>> but here you
>> have other factors to help you: the length of a typical PCB interconnect
>> trace becomes
>> such a small fraction of the wavelength that the impedance mismatch
>> simply wont matter.
>>
>> We also need to keep in mind that there are several factors that may add
>> to the complexity
>> of this picture or may mask out these trends altogether. The obvious
>> one is any discrete
>> discontinuity along the trace, like a via, but lets assume we rule those
>> out for now. Just
>> related to the uniform model, we still have surface roughness of the
>> conductors and the
>> glass-weave effect. These two factors will modify the above trends
>> somewhat, but will
>> not change the signs of the two slopes in the Zo(f) curve. For an
>> excellent summary on
>> these items you can look at the recent book: Stephen Hall, Howard Keck:
>> Advanced
>> Signal Integrity for High-Speed Digital Designs. IEEE-Wiley, 2009.
>>
>> The last item, which also might be bigger than any of the above, is the
>> potential nonuniformity
>> of the trace. Partly this may be related to the glass-weave effect, but
>> even more it is
>> due to differences in copper etching and differences in resin flow in
>> various parts of the
>> board, which will create different local dielectric constants (due to
>> different glass-resin ratio)
>> and different cross section geometries (trace width and layer height).
>> This non-consistency
>> from lot-to-lot and non-consistency within a panel are the major reasons
>> behind each PCB
>> fabricator's tolerance numbers. Typically 10% on inner layers and 15%
>> on outer layers.
>> These tolerance numbers assume very little if any variations due to
>> inductance and capacitance
>> variations, because those measurements assume the same methodology.
>> Wherever it may
>> fall on the frequency axis of a Zo(f) curve, from the same vendor it is
>> the same frequency
>> point for all measurements.
>>
>> Your questions are valid and represent the current challenges for many
>> of us in the industry.
>> This also reminds me how the important aspects have evolved over time.
>> When I started
>> to do signal-integrity courses almost twenty years ago, no-one cared yet
>> for dielectric loss,
>> or those few who already had this challenge, already knew enough about
>> it. As a result,
>> only a couple of hours from the full-week class had to be devoted to
>> trace losses. Ten
>> years ago people were interested in w-line models, but causality as a
>> requirement was
>> important for only a few applications. In contrast, more than half of
>> the latest class
>> material is touched one way or the other by the frequency dependent
>> nature of interconnects,
>> as this phenomenon penetrates more and more aspects of signal integrity.
>>
>> Finally, one of the few things that works in your favor in a lossy
>> interconnect, is the fact that
>> more losses will attenuate the reflected wave more, so eventually the
>> signal degradation
>> due to mismatch will be much less. With higher losses the Zo(f) curve
>> has more deviation
>> from nominal, but the resulting higher reflections may not matter. Or,
>> when you are lucky
>> enough to start with a low-loss scenario, the impedance variation does
>> not show up strongly
>> in the first place.
>>
>> Regards,
>>
>> Istvan Novak
>> SUN Microsystems
>>
>>
>>
>>
>>
>> Istvan Nagy wrote:
>>> Hi
>>>
>>> So, does it mean that we can not do anything useful about frequency
>>> dependent impedance control on digital boards?
>>> Impedance can vary 5% from 100MHz (analog VGA, reference clocks) to few
>>> GHz
>>> (PCI-express, SATA, XAUI), so it can cause a problem. Or that is the
>>> maximum
>>> accuracy what we can get?
>>> 5% unaccuracy is 5% extra mismatch for the termination, if we have other
>>> sources of a mismatch already (component tolerance). Isn't 5% bad, or is
>>> it
>>> acceptable?
>>>
>>> Another aspect is what single frequency to substitute for a digital
>>> signal
>>> for impedance/trace_width calculations/simulations?
>>> I thought it would be the knee frequency based on the signal's rise time,
>>> but i am not shure anymore.
>>> For 8b10b encoded signals, there should be a lower frequency
>>> (data_rate/10)
>>> limit in the signal's spectrum, since maximum 5 zeroes or ones can follow
>>> each other.
>>> Where do we need best matching for terminations, at the highest frequency
>>> components, or at the mean of the spectrum, or at the highest peak...?
>>> I was trying to do some simulations with different bit patterns in QUCS
>>> and
>>> cadence SigExplorer, then do FFT, but the result looks mostly meaningless
>>> garbage with some negative slope.
>>> Anyway, how does the spectrum looks like for real data signals,
>>> especially
>>> at the lower end of the spectrum?
>>>
>>> How does the TDR determine the impedance? Does it measure the reflected
>>> signal voltage peak?
>>> And at what frequency? if we check the impedance characteristics from DC
>>> to
>>> infinite Hz, the impedance varies a lot. In theory, if both a simulation
>>> and
>>> a TDR measurement gives a number, then at what frequency should they be
>>> equal, and why?
>>>
>>> regards,
>>> Istvan
>>>
>>>
>>> ----- Original Message -----
>>> From: "Mick zhou" <mick.zhou@xxxxxxxxx>
>>> To: "Yuriy Shlepnev" <shlepnev@xxxxxxxxxxxxx>
>>> Cc: "Istvan Nagy" <buenos@xxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>>> Sent: Monday, April 20, 2009 11:21 PM
>>> Subject: [SI-LIST] Re: TDR impedance measurement and rise time
>>>
>>>
>>>
>>>> Yurily,
>>>>
>>>> Nice study.
>>>> I'd like to bring it deeper if not re-invent the wheels.
>>>>
>>>> Except some practical issues, I think there is a fundamental issue
>>>> that is the definition of Z in t-domain and f-domain. The same
>>>> formula rho=(ZL-Z0)/(ZL+Z0) (or its V(t) form) is simply used in both
>>>> t- and f-domains. It does not matter if Z is f/t-independent,
>>>> otherwise it is questionable Unfortunately, it is the foundation of
>>>> most TDR algorithms so far. You can simply apply Fourier
>>>> transformation, convolution must be involved even we assume Z0 is a
>>>> constant. I don't know there is a good solution so far until we make
>>>> necessary corrections in the math.
>>>>
>>>> We may conclude that one to one match from f-domain to t-domain is
>>>> meaningless in general cases. That's probably the root cause of many
>>>> confusions. We can always find a point we like to have a "match".
>>>> For weak f-/t- dependent, it should be OK. Fortunately, most cases in
>>>> out community are weak f-/t- dependent? We don't need to worry as much
>>>> as we should?
>>>>
>>>> Thanks,
>>>>
>>>> Mick
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> 2009/4/8 Yuriy Shlepnev <shlepnev@xxxxxxxxxxxxx>:
>>>>
>>>>> Hi Istvan,
>>>>>
>>>>> Looking through this thread, I finally decided to spend a couple of
>>>>> hours
>>>>> and to do a simple numerical TDR experiment with a broad-band model of
>>>>> a
>>>>> micro-strip line segment, to see at least theoretical effect of the
>>>>> rise
>>>>> time and to correlate frequency-dependent characteristic impedance of
>>>>> the
>>>>> line with the values that can be observed on TDR. The results of this
>>>>> simple
>>>>> experiment are available as App. Note #2009_04 at
>>>>> http://www.simberian.com/AppNotes.php (no registration required). The
>>>>> conclusion is that the observed TDR impedance depends on the rise time
>>>>> and
>>>>> can be correlated with the characteristic impedance at different
>>>>> frequency
>>>>> bands (well, at least theoretically).
>>>>>
>>>>> Best regards,
>>>>> Yuriy Shlepnev
>>>>> www.simberian.com
>>>>>
>>>>>
>>>>> -----Original Message-----
>>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>>> On
>>>>> Behalf Of Istvan Nagy
>>>>> Sent: Tuesday, April 07, 2009 1:34 PM
>>>>> To: si-list@xxxxxxxxxxxxx
>>>>> Subject: [SI-LIST] Re: TDR impedance measurement and rise time
>>>>>
>>>>> Hi
>>>>>
>>>>>
>>>>> Peter from LeCroy wrote:
>>>>> "short impedance discontinuities... if you limit the frequency content
>>>>> ...,
>>>>> the bumps get smeared out by the slower risetime and they don't look so
>>>>> bad"
>>>>>
>>>>> - i think for these Test Coupon measurements is the point not to
>>>>> measure
>>>>> a
>>>>> real PCB trace with the lots of discontinuities, but to get the
>>>>> impedance
>>>>> based on the cross section. otherwise we would need different trace
>>>>> widths
>>>>> for every trace segment and we would need real-time 3D simulationd
>>>>> during
>>>>> PCB layout design.
>>>>>
>>>>> Exploring discontinuities on a real PCB (not on a test coupon) is is
>>>>> another
>>>>>
>>>>> story. I was asking about the measurements for the test coupons (maybe
>>>>> I
>>>>> forgot to mention). Normally (our) boards have hundreds of controlled
>>>>> impedance interconnects, those at the first place should be correct
>>>>> based
>>>>> on
>>>>>
>>>>> the cross section and test coupons. The rest is design practices, to
>>>>> make
>>>>> shure we dont deviate too much with discontinuitise. Of course its
>>>>> probably
>>>>> nice to characterise a full board, but in short development cycles, it
>>>>> wouldn't work very well. but i dont know, maybe it would...
>>>>>
>>>>> "Howard Johnson had an excellent video "
>>>>> - if anyone knows where to find it, i would appreciate...
>>>>>
>>>>>
>>>>> Jeff Loyer wrote:
>>>>> "The TDR will report the same characteristic impedance of your trace
>>>>> regardless of risetime"
>>>>>
>>>>> - which impedance? the impedance at 1 GHz? or at 10 GHz? or at xxx GHz?
>>>>> The characteristic impedance of a PCB trace depends on the frequency,
>>>>> since
>>>>> Er and the loss tangent are frequency dependent, and there is skin
>>>>> effect
>>>>> and others... so Z0(1GHz) is not equal to Z0(xxxGHz). So if a signal
>>>>> (lets
>>>>> simplify it) is at xxx GHz, then its terminations should be best
>>>>> matched
>>>>> at
>>>>> xxx GHz, and not at yyyGHz, so the board impedance should be correct at
>>>>> xxx
>>>>> GHz, and not at yyyGHz.
>>>>>
>>>>>
>>>>> Rob Sleigh wrote:
>>>>> "Yes, it's a very common practice to characterize a PDB with a TDR
>>>>> whose
>>>>> rise time is similar to the signal's rise time. It's up to the designer
>>>>> to
>>>>> decide, but usually pick a faster rise time than the system rise time
>>>>> to
>>>>> provide yourself with some margin."
>>>>>
>>>>> -most of the PCB manufacturers we talked to, they never asked about
>>>>> rise_time or frequency information of our signals, and when we tried to
>>>>> provide these to them they said they have deleoped their super-duper
>>>>> test
>>>>> setup which is based on tonns of measurements and it is accurate, and
>>>>> they
>>>>> dont care about our signal's frequency or rise time, and we should just
>>>>> pay
>>>>> and shut up... We tried In europe, north america and china. And the
>>>>> best
>>>>> what they say is they compensate for frequencies up to 10GHz, without
>>>>> knowing anything about our signal's freq/Tr.
>>>>> The last one said they can't or don't change rise times on their TDR...
>>>>>
>>>>>
>>>>> Kihong (Joshua) Kim wrote:
>>>>> "maximum frequency that may capture the bandwidth of imformation in
>>>>> digital
>>>>> world."
>>>>>
>>>>> - I was trying to estimate rise times and bandwidth. Especially at the
>>>>> receiver. I can't explain why it would be better than at the
>>>>> transmitter
>>>>> if
>>>>> they are both matched terminated to Z0, but I have a feeling like
>>>>> that...
>>>>> Normally at the receiver we have slower rise times. For example for
>>>>> PCIe
>>>>> and
>>>>>
>>>>> SATA, the signal looks sinusoid, not that rectangular as at the
>>>>> transmitter.
>>>>>
>>>>> So at a pattern 1010101010 the frequency would be fÚta_rate/2. For
>>>>> other
>>>>> interfaces, like DDR2/3, we can get rise times from simulation. So, I
>>>>> would
>>>>> provide these to the PCB manufacturer to calculate trace widths and
>>>>> verify
>>>>> by TDR/test-coupon measurements.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> regards,
>>>>> Istvan Nagy
>>>>> CCT, UK
>>>>>
>>>>>
>>>>> ----- Original Message -----
>>>>> From: "Kihong Joshua Kim" <joshuakh@xxxxxxxxx>
>>>>> To: "Nagy István" <buenos@xxxxxxxxxxx>
>>>>> Cc: <si-list@xxxxxxxxxxxxx>
>>>>> Sent: Tuesday, April 07, 2009 4:51 PM
>>>>> Subject: [SI-LIST] Re: TDR impedance measurement and rise time
>>>>>
>>>>>
>>>>>
>>>>>> Nagy,
>>>>>> Couple of TDR measurements experience for real boards with known trace
>>>>>> models and physical data will give you good sense of what TDR means.
>>>>>> However, if you do not have time to build sample boards nor have TDR
>>>>>> equipment...here is my help.
>>>>>>
>>>>>> Risetime conversion to frequency needs to be dealt with in-depth
>>>>>> understanding of the topic. The quick rule of thumb equation mentioned
>>>>>> in one of threaded mails is the maximum frequency that may capture the
>>>>>> bandwidth of imformation in digital world. This is weird part because
>>>>>> one
>>>>>> might has question on why I am talking about digital bandwith when
>>>>>> others
>>>>>> discuss about analog nature of signal (rise time). Some excercise to
>>>>>> uderstand Fourier analysis would give you an idea about what it meant.
>>>>>>
>>>>>> Anyhow, to get out of math and get the real sense of TDR with variety
>>>>>> of
>>>>>> sample boards.
>>>>>> I had developed couple of years ago a virtual TDR head (IBIS TDR
>>>>>> model) working just fine in any IBIS simualtion tools and I found out
>>>>>> the
>>>>>> paper in the internet (wow!). You could try sample boards as long as
>>>>>> you
>>>>>> have real board file and connector models and etc....
>>>>>>
>>>>>> If you google key words for IBIS TDR or TDR IBIS, you will find it
>>>>>> easily.
>>>>>> But just in case I attached here...
>>>>>>
>>>>>>
>>>>>>
>>>>> http://www.cadence.com/rl/Resources/conference_papers/stp_TDR_in_IBIS_Kim.pd
>>>>> f
>>>>>
>>>>>> Regards,
>>>>>>
>>>>>> Kihong (Joshua) Kim
>>>>>> http://www.linkedin.com/in/joshuakh
>>>>>>
>>>>>>
>>>>>>
>>>>>> On Tue, Apr 7, 2009 at 10:39 AM, Loyer, Jeff <jeff.loyer@xxxxxxxxx>
>>>>>> wrote:
>>>>>>
>>>>>>
>>>>>>> Concerning measuring Z0:
>>>>>>> The TDR will report the same characteristic impedance of your trace
>>>>>>> regardless of risetime, assuming your trace is long enough and there
>>>>>>> aren't
>>>>>>> significant variations in impedance along its length.
>>>>>>>
>>>>>>> Typically, we have very similar 6" coupons for all our controlled
>>>>>>> impedances. The board manufacturer will typically measure them with
>>>>>>> an
>>>>>>> HVM-compatible TDR, probably about 200 ps risetime. We verify the
>>>>>>> impedances with our ~17ps TDR.
>>>>>>>
>>>>>>> For simulations, on the other hand, you'll probably want a risetime
>>>>>>> faster
>>>>>>> than the projected risetime of your device (I'd guess about 2x; I
>>>>>>> don't
>>>>>>> remember seeing it quantified). I typically see folks just go with
>>>>>>> the
>>>>>>> risetime of the equipment, ~17ps, and ensure simulation match those
>>>>>>> measurements. They may be a little conservative, but probably less
>>>>>>> work
>>>>>>> in
>>>>>>> the long run than trying to exactly justify any particular risetime.
>>>>>>>
>>>>>>> The advantages/disadvantages I can think of off-hand for fast
>>>>>>> risetimes
>>>>>>> are:
>>>>>>> 1) fast R.T. = resolution of finer features (discontinuities).
>>>>>>> Unfortunately, this can also erroneously lead you to believe you need
>>>>>>> to
>>>>>>> fix things that are "invisible" at your risetime of interest.
>>>>>>> Filtering
>>>>>>> to
>>>>>>> your risetime of interest can help you decide whether a discontinuity
>>>>>>> is
>>>>>>> significant or not.
>>>>>>> 2) fast R.T. = smaller probing geometries. It doesn't make sense to
>>>>>>> try
>>>>>>> to
>>>>>>> maintain a 15 ps risetime through a launch structure with 30 mil vias
>>>>>>> spaced
>>>>>>> 100 mils apart (such as might be used for manufacturing testing).
>>>>>>> Living
>>>>>>> with slower risetimes can allow you to adopt much more HVM-friendly
>>>>>>> launch
>>>>>>> structures, including pogo-pinned probe connections.
>>>>>>> 3) fast R.T. = less ESD protection. It's very easy to damage a TDR
>>>>>>> head
>>>>>>> from static discharge - HVM-compatible TDR machines with slower
>>>>>>> risetimes
>>>>>>> have ESD protection.
>>>>>>>
>>>>>>> If the scope or post-processing software doesn't have the ability to
>>>>>>> slow
>>>>>>> your risetimes, you can buy filters from Picosecond Pulse labs (buy a
>>>>>>> filter
>>>>>>> at 0.35/RT). They also sell hardware to put out very fast risetimes.
>>>>>>>
>>>>>>> Jeff Loyer
>>>>>>>
>>>>>>> -----Original Message-----
>>>>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>>>>> On Behalf Of Nagy István
>>>>>>> Sent: Tuesday, April 07, 2009 4:59 AM
>>>>>>> To: si-list@xxxxxxxxxxxxx
>>>>>>> Subject: [SI-LIST] TDR impedance measurement and rise time
>>>>>>>
>>>>>>> hi
>>>>>>> If we measure PCB test coupons with a TDR to determine characteristic
>>>>>>> impedance, should we set the rise time to be the same as the signal's
>>>>>>> rise
>>>>>>> time? is it possible to set it at all?
>>>>>>>
>>>>>>> what i found on the internet, the TDR manufacturers try to make rise
>>>>>>> time
>>>>>>> to be as low as possible, like 15ps..., and thats it.
>>>>>>>
>>>>>>> If the rise time is always 15ps, then i think it will always measure
>>>>>>> the
>>>>>>> impedance on a very high frequency, 2/t_rise or something, so several
>>>>>>> gigahertz. Usually on a board we have different signals, some are
>>>>>>> running
>>>>>>> 100MHz analog, some other are 800MT/s digital, or 2.5Gb/s digital.
>>>>>>> shouldn't we do different setups for these, to get impedances on the
>>>>>>> signal's operating frequency?
>>>>>>>
>>>>>>> Someone from a Fab told me, that the "TDR is not frequency
>>>>>>> dependent".
>>>>>>> so
>>>>>>> they dont take the signal's frequency into account.
>>>>>>>
>>>>>>> what is the correct handling of signaling frequency for impedance
>>>>>>> measurements, and simulations?
>>>>>>>
>>>>>>> regards,
>>>>>>>
>>>>>>> Istvan Nagy
>>>>>>> CCT
>>>>>>>
>>>>>>>
>>
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