[SI-LIST] Re: TCOmin < external buffer delay
- From: Ihsan Erdin <erdinih@xxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>
- Date: Fri, 21 Oct 2005 08:12:27 -0400
Hi Steve,
Sorry for my empty message. Although I've always been a bit leery about
this kind of behavioral modeling that merely depends on a set of numbers
under restricted conditions, I think this whole IO buffer standardization
should cover these issues as well. If not, we should restrict the usage of
these models to signal integrity for overshoot/undershoot, termination
requirements, etc. Timing is too serious an issue to go with uncertainty in
a digital circuit...
Ihsan
On 10/20/05, steve weir <weirsi@xxxxxxxxxx> wrote:
>
> Ishan, while what you say about buffer construction is true, it really
> doesn't go to Andy's point which my interpretation is:
>
> KNOW YOUR MODEL'S FRAME OF REFERENCE!
>
> One would hope that the model maker constructed the model in question such
> that it can be correlated to observable nodes on the board. But there
> isn't anything that forces them to be so reasonable.
>
> Steve.
>
> At 09:32 PM 10/20/2005 -0400, Ihsan Erdin wrote:
> >In contemporary IC devices, the buffer stage operation is distinctly
> >separated from that of the core logic. IO buffers are multistage analog
> >(OPAMP) amplifiers that interface to the core logic with a differential
> >amplifier stage. Their output stage is a highly linear class-AB amplifier
> >with a low impedance to drive the load. They are usually operated at
> higher
> >voltage levels than the core circuit because in microprocessors and such,
> >the internal logic has to switch at much higher rates than the output,
> hence
> >the necessity of lower voltage levels at the core. With the advent of low
> >voltage signaling like LVDS, PECL, HSTL, etc. for gigabit interfaces,
> >devices that employ them have started to operate at the same voltage as
> the
> >core but that doesn't merge the IO and core logic. In this context,
> >subtracting the buffer delay from the output timing is justified for the
> >accuracy of timing analysis.
> >As for the cases where buffer delay may be larger than the min. output
> >timing parameter, we know for sure that the data cannot be at the buffer
> >output before the min delay following the clock edge. Rounding the
> internal
> >logic delay to zero will yield a higher than spec'd min output time,
> which
> >may mess up the whole fast process timing computations. So using the
> >negative number is the right thing to do.
> >
> >Ihsan Erdin
> >Nortel
> >
> >On 10/20/05, Andrew Ingraham <a.ingraham@xxxxxxxx> wrote:
> > >
> > > > According to the TCO measurement, TCO include Internal
> > > > Logic delay and external buffer delay.
> > >
> > > I am assuming by "external buffer" you mean the buffer, internal to
> your
> > > device, that drives the output (external) signal. Is that what you
> meant?
> > >
> > > > I use the IBIS model and the measurement circuit to
> > > > measure the external buffer delay.
> > >
> > > Be careful about this. IBIS does not necessarily model the external
> buffer
> > > delay. The IBIS model may represent just a portion of the buffer, or
> it
> > > may
> > > include more than the buffer. All you know is that IBIS describes how
> the
> > > buffer drives the output node. If you set up a simulation and measured
> the
> > > delay from the "input" of the IBIS model to its output, it is a
> relatively
> > > meaningless measurement.
> > >
> > > Aside from that, there are many reasons why the internal logic would
> > > appear
> > > to have a negative delay. One is if the device incorporates a PLL for
> the
> > > clocks. Another happens because of different loading conditions. If
> your
> > > calculation results in a negative number and you know you are doing
> the
> > > right calculations and using the right methods, then use the negative
> > > number, not zero.
> > >
> > > Why do you need to separate the internal logic delay from the output
> > > buffer,
> > > anyway? Why not just treat your device as one block that has no such
> > > boundary? (Perhaps my assumption above was incorrect?)
> > >
> > > Regards,
> > > Andy
> > >
> > > ------------------------------------------------------------------
> > > To unsubscribe from si-list:
> > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > >
> > > or to administer your membership from a web page, go to:
> > > //www.freelists.org/webpage/si-list
> > >
> > > For help:
> > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > > List FAQ wiki page is located at:
> > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > >
> > > List technical documents are available at:
> > > http://www.si-list.org
> > >
> > > List archives are viewable at:
> > > //www.freelists.org/archives/si-list
> > > or at our remote archives:
> > > http://groups.yahoo.com/group/si-list/messages
> > > Old (prior to June 6, 2001) list archives are viewable at:
> > > http://www.qsl.net/wb6tpu
> > >
> > >
> > >
> >
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> >or to administer your membership from a web page, go to:
> >//www.freelists.org/webpage/si-list
> >
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List FAQ wiki page is located at:
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> >
> >List technical documents are available at:
> > http://www.si-list.org
> >
> >List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> >Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
