Andy: Some SI tools, like Cadence Allegro PCB SI, subtract buffer delay from switching and settling times if you decide you want it to. The buffer delay is the time when the buffer starts to rise (or fall) at the output to Vmeasure into the standard load defined in the IBIS file with Vref, Rref, and Cref. Since the Tco number is defined into the same standard load, this allows you to avoid double counting the standard load delay in your timing equations. This is a fairly subtle concept that has to be learned to get accurate timing numbers from IBIS simulators. The trouble is that when Vdd changes with slow and fast cases, the tool doesn't take that into account in calculating buffer delay. For most slower logic, this is not an issue. When looking at near GHz GDDR interfaces, you need to run 3 different batch jobs to get the three corner cases properly. Cheers, -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Andrew Ingraham Sent: Thursday, October 20, 2005 11:56 AM To: SI freelist Subject: [SI-LIST] Re: TCOmin < external buffer delay > According to the TCO measurement, TCO include Internal > Logic delay and external buffer delay. I am assuming by "external buffer" you mean the buffer, internal to your device, that drives the output (external) signal. Is that what you meant? > I use the IBIS model and the measurement circuit to > measure the external buffer delay. Be careful about this. IBIS does not necessarily model the external buffer delay. The IBIS model may represent just a portion of the buffer, or it may include more than the buffer. All you know is that IBIS describes how the buffer drives the output node. If you set up a simulation and measured the delay from the "input" of the IBIS model to its output, it is a relatively meaningless measurement. Aside from that, there are many reasons why the internal logic would appear to have a negative delay. One is if the device incorporates a PLL for the clocks. Another happens because of different loading conditions. If your calculation results in a negative number and you know you are doing the right calculations and using the right methods, then use the negative number, not zero. Why do you need to separate the internal logic delay from the output buffer, anyway? Why not just treat your device as one block that has no such boundary? (Perhaps my assumption above was incorrect?) Regards, Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu