[SI-LIST] Re: TCOmin < external buffer delay
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: "SI freelist" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Oct 2005 11:56:29 -0400
> According to the TCO measurement, TCO include Internal
> Logic delay and external buffer delay.
I am assuming by "external buffer" you mean the buffer, internal to your
device, that drives the output (external) signal. Is that what you meant?
> I use the IBIS model and the measurement circuit to
> measure the external buffer delay.
Be careful about this. IBIS does not necessarily model the external buffer
delay. The IBIS model may represent just a portion of the buffer, or it may
include more than the buffer. All you know is that IBIS describes how the
buffer drives the output node. If you set up a simulation and measured the
delay from the "input" of the IBIS model to its output, it is a relatively
meaningless measurement.
Aside from that, there are many reasons why the internal logic would appear
to have a negative delay. One is if the device incorporates a PLL for the
clocks. Another happens because of different loading conditions. If your
calculation results in a negative number and you know you are doing the
right calculations and using the right methods, then use the negative
number, not zero.
Why do you need to separate the internal logic delay from the output buffer,
anyway? Why not just treat your device as one block that has no such
boundary? (Perhaps my assumption above was incorrect?)
Regards,
Andy
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