[SI-LIST] Re: Switching FET Slew Rate
- From: <npatel@xxxxxxxxxx>
- To: <adayjoseph-lists@xxxxxxxxx>
- Date: Fri, 20 Jul 2007 15:49:03 -0600
In the past to reduce EMI out of SMPS I have added resistance to the
gate of the FET and had very good luck with it. However this causes
thermal issues. Check FET specs for thermal compliance.=20
Nikhil
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joseph Aday
Sent: Friday, July 20, 2007 3:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Switching FET Slew Rate
Hi All,
=20
I am curious to see if anyone has an opinion on the best way to slow
down the slew rate of a FET in a switching power supply. =20
=20
One way is to add a series termination resistor at the final output,
but this would change the DC power level since it affects the DC drive
stength. =20
A second way is to add some source resistance to the FET. This seems
to be effective.
=20
I'd love to hear others' opinions / experiences, if any? This is
intended to be an open question, not necessarily specific to any design.
=20
Thank you,
Joseph Aday
=20
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=20
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