[SI-LIST] Re: Strange resets happening in one of our circuit boards
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 2 Jun 2006 23:43:02 -0400
> Even though reset durations may be long, you still need to bring
> everybody out of reset in a timely fashion.
...
> Thus the asserting edge of reset might be slow, but the negating
> edge may need to be faster.
And in other cases the asserting edge needs to be reasonably fast too.
Sometimes it's necessary to "get everyone off the bus" (disable all output
buffers) quickly. "Quickly" here may mean on the order of 10s of
nanoseconds; not exactly lightning fast, but not so slow that you don't care
either.
The designer needs to understand the system's requirements, specifications,
and Reset timing. Each case may be different.
Regards,
Andy
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