[SI-LIST] Re: Stitching Vias
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 08 Mar 2012 21:21:28 -0800
This addresses most of your immediate questions on behaviors:
http://www.ipblox.com/pubs/SVCEMC_Feb_2012/How Bad is Bad.pdf Your
quantitative questions require that you do engineering homework.
Today, there are lots of good books out there on the subjects of power
and signal integrity. Get a hold of one and start reading.
Steve.
On 3/8/2012 8:11 PM, krishna@xxxxxxxxxxxxxxxxxxx wrote:
> Hi ALL
>
>
> I am new to the concept of Stitching Vias and capacitances in PCBs.
>
> Hence I request the experts in this forum to help me understand the
> following:
>
>
>
> 1. What are stitching vias?
> 2. Why are they needed?
> 3. How to determine how many stitching vias are required for a given
> layer stack up and signals?
> 4. How far or close they should be to the signal vias if they are to be
> decided with respect to the location of signal vias?
> 5. One Layout Engineer was recently talking about stitching
> capacitances in the inner layers for making the power planes to behave like
> a good reference plane (similar to a ground plane)? I couldn't understand
> what he was talking about. Please help.
> 6. Is stitching capacitance same as stitching vias? When are they
> needed.
> 7. Are there any reference texts or app notes available to know these
> things?
>
>
>
> Please help.
>
>
>
> Thank you very much,
>
>
>
> With Thanks and Best Regards,
>
> Krishna.
>
>
>
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--
Steve Weir
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